PM73121 Datasheet, PDF (195/223 Pages) PMC-Sierra, Inc – AAL1 Segmentation And Reassembly Processor

Data Sheet
PMC-980620
,VVXH 
PMC-Sierra, Inc.
PM73121 AAL1gator II
AAL1 SAR Processor
8.6.3 SRAM with 8 ns Write Data Setup and a TTL Clock
When using a TTL clock with an SRAM with a 8 ns setup requirement, the clock duty cycle
requirement is very tight. One way to tighten up the duty cycle of a clock is to derive the clock
from a higher frequency. Since each edge will be evenly spaced, the only way to affect symmetry
is to adjust the difference in the rise and fall time at 1.5 V.
Assuming we want to have a 0.5 ns margin on both setup and hold time, the requirements to meet
are:
Tch_min - 4.3 + Rs ≥ 8.5 ns
Tp - Tch_max - Rs -10 ≥ 0.5 ns
A 1% duty cycle TTL clock source at 38.88 MHz has a Tch_min of 12.6 ns and a Tch_max of 13.1 ns.
Replacing Tch_min and Tch_max in the equations above gives:
Rs ≥ 8.5 + 4.3 -12.6 ≥ 0.2 ns
Rs ≤ 25.7 - 13.1 - 10 - 0.5 ≤ 2.1 ns
Referring to Table 24 on page 175 shows that selecting a 50 Ω resistor would meet both
requirements.
In summary, one possible solution when using an SRAM with 8 ns setup is to use a 1% duty cycle
TTL clock source and a 50 Ω series resistor. To increase the margin, a higher value resistor or a
CMOS clock driver could be used. A resistor value greater than 100 Ω should not be used since
this will cause rise/fall times that are too slow and will not match the board impedance close
enough. The rise/fall time of the clock should be less than 1.5 ns.
8.6.4 SRAM with 8 ns Write Data Setup and a CMOS Clock
When using a CMOS clock, the rise and fall time of the clock needs to be considered to determine
the pulse width at a TTL level. The benefit of using a CMOS clock is that the pulse width will be
wider at the TTL level than at the CMOS level. Rise/fall times for CMOS outputs are usually
given from the 20% to the 80% level, or across a 3 V range. Dividing this number by 3 gives the
approximate delay between the 1.5 V level and the 2.5 V level. Since the delay occurs at both
rising and falling edges, this value is doubled to give the increase in setup time. Usually the
critical factor with a CMOS clock driver is the hold time.
For example, if the rise/fall time is 3 ns, there will be a 1 ns delay from a transition at 1.5 V to the
transition at 2.5 V, and a 2 ns increase in setup time.
Assuming we want a 0.5 ns margin on both setup and hold time, the requirements to meet are:
Tch_min - 4.3 + Rs ≥ 8.5 ns
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