PM6541 Datasheet, PDF (10/49 Pages) PMC-Sierra, Inc – E1XC EVALUATION DAUGHTERBOARD

TELECOM STANDARD PRODUCT
PMC-930917
ISSUE 1
PMC-Sierra, Inc.
PM6541 E1XC-EVBD
E1XC EVALUATION DAUGHTERBOARD
AD[1]
AD[0]
PA3
PA4
PA5
PA6
PD2
PD3
PD4
PD5
IRQ
XIRQ
DISB
SP
GND
+5V
I/O C19 Multiplexed address/data bus bit 1
I/O C20 Multiplexed address/data bus bit 0
O C21 68HC11 Processor Port A bit 3
O C22 68HC11 Processor Port A bit 4
O C23 68HC11 Processor Port A bit 5
O C24 68HC11 Processor Port A bit 6
I C25 MISO. Master In Slave Out of Port D acting as SPI.
Pulled up on motherboard.
O C26 MOSI. Master Out Slave In of Port D acting as SPI.
Pulled up on motherboard.
O C27 SCK. Serial clock of Port D acting as SPI. Pulled up
on motherboard.
O C28 SS. Slave Select of Port D acting as SPI active low.
Pulled up on motherboard.
I C29 Maskable interrupt
I C30 Non Maskable Interrupt
I C31 EVMB memory disable. Pulling this signal low will
disable MPU access to the EVMB's on-board RAM
and EPROM.
O C32 SPARE
O A1- Ground
A28
O A29- +5 Volts
A32
3.2 Header Connections
All E1XC functional pins are connected to male header strips to provide as much
access as possible. These headers may be used as probe points or as a means to
build sample applications by making appropriate connections between points. Each
E1XC can run in isolation of the other, thus any application, other than the default
sample "CSU", will require header connections to be made.
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