RM7935 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 64-bit Microprocessors with Integrated L2 Cache and EJTAG

RM7935/RM7965
64-bit Microprocessors with Integrated L2 Cache and EJTAG
PRODUCT HIGHLIGHTS
• New high performance MIPS64-compatible Instruction Set
Architecture with integrated L2 cache and EJTAG:
• 668, 750, 835 and 900 MHz operating frequency.
• 1890 Dhrystone 2.1 MIPS @ 900 MHz.
• Dual-issue superscalar 7-stage pipeline.
• 16 Kbyte, 4-way set associative L1 Instruction cache.
• 16 Kbyte, 4-way set associative L1 Data cache.
• 256 Kbyte, 4-way set associative L2 cache with industry best 5-
cycle access latency.
• Fast Packet Cache to assists processing of packet data.
• 8K entry branch prediction table.
• Fully associative 64-entry TLB with dual pages.
• High-performance Floating Point Unit (IEEE 754).
• Fixed-point DSP instructions such as Multiply/Add,
Multiply/Subtract, and 3 Operand Multiply.
BLOCK DIAGRAM
Released
Product Brief
• High-performance system interface:
• 32-bit multiplexed address/data (SysAD) bus with RM7935.
• 64-bit SysAD with RM7965.
• Multiple outstanding reads with out-of-order return.
• 1600 Mbyte/s peak throughput.
• 200 MHz maximum frequency using HSTL signaling on the SysAD
bus.
• SysAD bus supports 1.5 V, 2.5 V, 3.3 V I/O logic.
• Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8,
8.5, 9, 10, 11, 12, 13, 14, 15, 16, 17.
• Integrated on-chip EJTAG capability.
• A 64-entry dynamic Trace Buffer for use in real-time trace and
debug.
• Two 32-bit virtually-addressed Watch registers.
• Integrated performance counters:
• 2 independent 32-bit counters.
• Counts over 30 processor events including miss predicted
branches.
• Enables full characterization and analysis of application
software.
64-bit Integer Unit
Dual-Issue Superscalar
Integer Multiplier
On-Chip Debug
Branch Trace Buffer
64-bit Floating Point Unit
Double/Single IEEE-754
Instruction Dispatch
Instruction Cache
16 KB, 4-way
Line Lockable
8K Entry Branch History Tbl
Memory Manager
64-Entry, Dual Page
Data Cache
16 KB, 4-way
Line Lockable
Interface Unit
SysAD
System Interface
System Control
Secondary Cache
256 KB, 4-way
Line Lockable
E9000 Core
Interrupt
Interface
EJTAG/JTAG
Controller
Cache Test
Mode
PLL & Clock
PMC-2030350, Issue 4
© Copyright PMC-Sierra, Inc. 2003–2006
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.