PM8372 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 4-Port FC/GE Retimer and FC-AL Port Bypass Controller

4-Port FC/GE Retimer and FC-AL Port Bypass Controller
PM8372
PBC 4x2G
Preview
GENERAL
• Supports 4 Fibre Channel Physical
Interfaces at 1.0625 or 2.125 Gbit/s
per Fibre Channel – Physical Interface
(FC-PI) or 4 Gigabit Ethernet Retimers
at 1.25 Gbit/s per IEEE 802.3z.
• Each port supports FC 1G or 2G rate
detection/auto-selection.
• Supports Arbitrated Loop and Retimer
configuration.
• Each port is independently selectable
to perform retimer, reclocker or
bypass-path function.
• Non-blocking crossconnect supports
protection switching, broadcasting and
multicasting.
• Automatic selection of retimer,
reclocker or bypass-path function to
minimize latency and jitter when a disk
is bypassed.
• Per-port receive monitoring for loss of
signal, error rate, and link level
violations.
• Supports single-ended or differential
106.25 MHz reference clock REFCLK
for Fibre Channel applications or
125 Mhz reference clock for Gigabit
Ethernet applications.
HIGH-SPEED INTERFACE
• High-speed outputs with selectable pre-
emphasis per port to counteract
dielectric losses and allow maximum
reach on printed circuit boards.
• Selectable receive input equalization for
improved signal integrity.
• Minimized board footprint and improved
signal integrity achieved because:
• No external components are required
to interface the high-speed signals to
optics, coax, or serial backplanes
using the internal AC coupling
capacitors and terminating resistors.
• Receive input termination of 100 Ω or
150 Ω differential is selectable.
• Source output impedance of 100 Ω or
150 Ω differential is programmable.
TEST AND CONTROL
• Supports optional 2-pin serial
management interface using selectable
Two-Wire Interface (TWI) or MDC/MDIO
protocol for configuration and diagnostic
access.
• For normal mode of operation, a
management interface is not required.
• Digital Loss of Link (DLOLB) detect
outputs for monitoring individual or
multiple links. DLOLB can be
programmed to indicate excessive
8B/10B code error rate, loss of
synchronization, loss of signal, CRC32
errors, or comma density.
• Interrupt output to flag changes in
bypass state and DLOLB error
conditions.
• Supports built-in self-test (BIST) via
internal Fibre Channel pattern
generation and checking.
• External control pins can be overwritten
by registers.
BLOCK DIAGRAM
TDOP[2]
TDON[2]
2
RDIP[1]
RDIN[1]
2
TDOP[1]
TDON[1]
2
RDIP[0]
RDIN[0]
2
TCK
TMS
TDI
TDO
TRSTB
SERDES/
Reclocker
Tx
10 _Control
Rx
Retimer/
Monitor
10
SERDES/
Reclocker
Tx
10 _Control
Rx
Retimer/
Monitor
10
Loopback/
Failover
Cross
Connect
CDRU
Impedance
Control
Two Wire
Interface
Rx
Retimer/
Monitor
10
Tx
Control ¹⁰
SERDES/
Reclocker
Rx
Retimer/
Monitor
10
Tx
Control ¹⁰
SERDES/
Reclocker
Pattern
Generator/
Comparator
2
RDIP[2]
RDIN[2]
2
TDOP[3]
TDON[3]
2
RDIP[3]
RDIN[3]
2
TDOP[0]
TDON[0]
Control Block
DLOLB
PORT_DLOLB[3:0]
INTRB
PMC-2021698
Issue 2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2003.
All rights reserved.