PM7381 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 32 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE

PMC-Sierra,Inc.
Frame Engine and Data Link Manager
PM7381
FREEDM-32A672
FEATURES
The FREEDM-32A672 chip offers
the following features:
• Single-chip multi-channel HDLC
controller with a 50 MHz, 16-bit
Any-PHY Packet Interface (APPI)
for transfer of packet data using an
external controller. Each APPI bus
can support up to seven
FREEDM-32A672 devices to
enable high-density and
low-latency applications.
• Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 32 H-MVIP digital
telephony buses at 2.048 Mbit/s
per link, or 8 H-MVIP buses at
8.192 Mbit/s per link.
• Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 32 channelized T1/
J1/E1 links. You can program the
number of time-slots assigned to
an HDLC channel from 1 to 24 (for
T1/J1) and from 1 to 31 (for E1).
• Supports up to 32 bi-directional
HDLC channels, each assigned to
an unchannelized arbitrary-rate
link, subject to a maximum
aggregate link clock-rate of 64
MHz in each direction.
• Channels assigned to links 0 to 2
support clock rates up to 52 MHz.
Channels assigned to links 3 to 31
support clock rates up to 10 MHz.
In the special case, where no
more than 3 high-speed links are
used, the maximum aggregate link
clock-rate is 156 MHz.
• Links configured for channelized
T1/J1/E1 or unchannelized
operation support the
gapped-clock method for
determining time-slots, which is
backwards compatible with the
FREEDM-8 and FREEDM-32
devices.
• For each channel, the HDLC
receiver supports programmable
flag-sequence detection, bit
de-stuffing and frame-check
sequence validation. The receiver
supports the validation of both
CRC-CCITT and CRC-32
frame-check sequences.
• For each channel, the HDLC
transmitter supports
programmable flag-sequence
generation, bit stuffing and
frame-check sequence
generation. The transmitter
supports the generation of both
CRC-CCITT and CRC-32
frame-check sequences. The
BLOCK DIAGRAM
RD[31:0]
RCLK[31:0]
RFPB[3:0]
RMVCK[3:0]
RMV8DC
RMV8FPC
RFP8B
TD[31:0]
TCLK[31:0]
TFPB[3:0]
TMVCK[3:0]
TMV8DC
TMV8FPC
TFP8B
Receive
Channel
Assigner
(RCAS672)
Transmit
Channel
Assigner
(TCAS672)
Receive
HDLC
Processor
(RHDL672)
32 k Receive
Partial
Packet
Buffer
Performance
Monitor
(PMON)
Transmit
HDLC
Processor
(THDL672)
32 k Transmit
Partial
Packet
Buffer
Microprocessor
Interface
JTAG
Receive
Any-PHY
Packet
Interface
(RAPI672)
Transmit
Any-PHY
Packet
Interface
(TAPI672)
RXCLK
RXADDR[2:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RSX
REOP
RMOD
RERR
RVAL
TXCLK
TXADDR[12:0]
TPA1[2:0]
TPA2[2:0]
TRDY
TXDATA[15:0]
TXPRTY
TSX
TEOP
TMOD
TERR
PMC-1980428 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © 2001 PMC-Sierra, Inc.