PM7342 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY

Preliminary
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
PM7342
S/UNI®-IMA-32
FEATURES
IMA
• Supports up to 32 T1, E1, G.SHDSL or
unchannelized links and up to 32 IMA
groups with 1 to 32 links/group.
• Link and Group State Machines
implemented on-chip requiring no real
time software in the data path.
• Fully compliant with the ATM Forum
Inverse Multiplexer for ATM (IMA)
1.1 specification and backward
compatible to IMA 1.0.
• Supports both independent transmit
clock (ITC) and common transmit clock
(CTC) modes.
• Supports all IMA Group Symmetry
modes: Symmetric/Asymmetric
configuration and operation.
• Differential delay tolerance of 279 ms
(for T1 links) and 226 ms (for E1 links).
• Performs IMA differential delay
calculation and synchronization.
• Provides programmable limit on
allowable differential delay and
minimum number of links per group.
• Performs ICP and stuff-cell insertion
and removal.
• Supports IMA frame length (M) equal
to 32, 64, 128, or 256.
• Provides IMA layer statistic counts and
alarms for support of IMA Performance
and Failure Alarm Monitoring and MIB
support.
• Provides per link counters for statistics
and performance monitoring.
UNI
• Each link is software configurable as
either a UNI or part of an IMA group.
• Performs receive cell Header Error
Check (HEC) checking and transmit
cell HEC generation.
• Optionally supports receive cell
payload unscrambling and transmit cell
payload scrambling.
• Provides TC layer statistics counts and
alarms for MIB support.
ATM OVER FRACTIONAL T1/E1
• Supports ATM over Fractional T1/E1
compliant with the ATM Forum
AF-PHY-0130.00 specification.
BLOCK DIAGRAM
LINE INTERFACE
• 32 T1, E1, G.SHDSL or unchannelized
links via 2-pin line interfaces.
• Supports a 19.44 MHz Scalable Band-
width Interconnect (SBI) bus interface for
seamless interconnect to the PM8315
TEMUX and PM8316 TEMUX-84.
• SBI supports two Synchronous
Payload Envelopes (SPE). Each SPE
can carry up to 16 T1s or 16 E1s.
UTOPIA / ANY-PHY INTERFACE
• Supports 8- and 16-bit UTOPIA L2 and
Any-PHY cell interfaces at clock rates
up to 52 MHz.
• Any-PHY transmit slave appears as a
32 port multi-PHY. The PHY-ID of
each cell is identified using in-band
addressing.
• Any-PHY receive slave appears as a
single device. The PHY-ID of each cell
is identified using in-band addressing.
• UTOPIA L2 transmit and receive slave
appears as a 31-port multi-PHY.
• UTOPIA L2 receive slave can also
appear as a single port with the logical
port provided as a prepend.
SBI Add Bus I/F
AC1FP
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
AACTIVE
ADETECT
32 Clk/Data
TSCLK[31:0]
TSDATA[31:0]
CTSCLK
INSBI
Null
Framer
(SDFR32)
TCAS
TC Layer
(TTTC32)
32 Clk/Data
RSCLK[31:0]
RSDATA[31:0]
SBI Drop Bus I/F
DC1FP
DDATA[7:0]
DDP
DPL
DV5
RCAS
EXSBI
De-
Framer
(SDDF32)
TC Layer
(RTTC32)
DLL
MicroProcess I/F
32-chan
x 7 cell
FIFO
(MCFD)
Tx IMA Processor
(TIMA)
IDCC
JTAG
32-chan
x
3 cell
FIFO
Any-PHY/
UTOPIA
Tx Slave
(TXAPS)
Tx Slave
ATM I/F
TCLK
TPA
TENB
TADR[10:0]
TCSB
TSOP
TSX
TDAT[15:0]
TPRTY
Internal Bus
IDCC
Rx IMA
Protocol
Processor
(RIPP)
32-chan
x 2 cell
FIFO
Rx IMA
Data Processor
(RDAT)
Cell Writer
Cell Reader
Memory Interface
(MEMI)
31
chan
4 cell
FIFO
Any-PHY/
UTOPIA
Rx Slave
(RXAPS)
Rx Slave
ATM I/F
RCLK
RPA
RENB
RADR[4:0]
RCSB
RSOP
RSX
RDAT[15:0]
RPRTY
PMC-2001523 (p5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2002