PM5392 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – SATURN User Network Interface for 9.953 Gbit/s

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PM5392
S/UNI®-9953-POS
SATURN® User Network Interface for 9.953 Gbit/s
GENERAL DESCRIPTION
• The S/UNI-9953-POS is a single chip
ATM, POS User-Network Interface
operating at 9953.28 Mbit/s. The S/UNI
9953-POS is intended for use in OC-
192c and high-density OC-48c
POS/ATM applications.
FEATURES
• Supports framing, scrambling/
descrambling and pointer processing
for the following:
• STS-192c (STM-64-64c).
• 4 x STS-48c (4 x STM-16-16c).
• STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
• Supports alarm signal
insertion/detection, B1/2/3 processing
and insertion/termination of SONET
Section/Line/Path overhead bytes (or
SDH equivalents).
• Provides ATM and POS payload
processing for:
• STS-192c (STM-64-64c)
• 4 x STS-48c (4 x STM-16-16c).
• STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
INTERFACES
• Provides SATURN® POS-PHY™
Level 4 16-bit LVDS System-side
Interface (clocked at 700 MHz
nominal).
• Directly connects to optics via 16 bit by
622 MHz OIF SFI-4 (OIF99.102) line-
side interface.
POS/ATM
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT
Recommendation I.432.
• Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
GENERAL
• Provides internal FIFOs (16 KB
ingress, 20 KB egress) to
accommodate system latencies.
• Provides line-side and system-side
loopbacks for system level diagnostic
capability.
• Provides support for automatic
protection switching (APS) via two 16-
bit LVDS 777.76 MHz ports.
• Provides a generic 16-bit
microprocessor bus interface for
configuration, control and status
monitoring.
• Standard 5 signal P1149.1 JTAG test
port.
BLOCK DIAGRAM
RXDATA+/-
RXCLK+/-
SFI-4
Rx
Interface
TXCLK+/-
TXDATA +/-
TXCLK_SRC+/-
SFI-4
Tx
Interface
Rx SONET
BER
Monitor
LVDS I/F
APS
Rx
Transport
O/H
Processor
Rx Path
O/H
Processor
Rx Payload
Aligner
Rx Cell/
Frame
Processor
Ingress POS-PHY
Flexible Level 4
FIFO Interface
RSTAT
RSCLK
RCTL+/-
RDAT+/-
RDCLK +/-
PL4 REF +/-
Tx
Transport
O/H
Processor
Tx High-
Order Path
O/H
Processor
Tx Cell/
Frame
Processor
Egress POS-PHY
Flexible Level 4
FIFO Interface
TDCLK +/-
TDAT+/-
TCTL+/-
TSTAT
TSCLK
APS
LVDS I/F
Microprocessor
JTAG
PMC-2010908 (A1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
 Copyright PMC-Sierra, Inc. 2001