PM5357-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 622 Mbit/s ATM and Packet Over SONET Physical Layer Device

PMC-Sierra,Inc.
PM5357
S/UNI-622-POS
622 Mbit/s ATM and Packet Over SONET Physical Layer Device
FEATURES
GENERAL
• ATM and Packet over SONET/SDH
(POS) OC-12c (622 Mbit/s) PHY
• Provides on-chip clock and data
recovery and clock synthesis
• Exceeds Bellcore-GR-253 jitter
requirements
• Inserts and extracts ATM cells or POS
packets into/from SONET SPE
• Filters and captures Automatic
Protection Switch bytes (K1,K2) and
detects APS byte failure
• Detects signal degrade and signal
failure thresholds crossing alarms
• Captures and debounces
synchronization status byte (S1)
• Extracts and Inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages
• Extracts and inserts section/line data
communication channels (DCC)
• Provides circuitry to meet holdover,
wander and long term stability
• Provides a generic 8-bit
microprocessor interface for device
control and register access
• Provides standard IEEE 1149.1 JTAG
test port for boundary scan
ATM
• Implements the ATM Forum User
Network Interface Specification
• Performs cell payload scrambling and
descrambling
• Provides a UTOPIA Level 2 and an 8-
bit 100MHz UTOPIA Level 3 compliant
system interface
• Provides synchronous 4 cell transmit
and receive FIFO buffers
PACKET OVER SONET/SDH
• Supports direct packet mapping into
SONET/SDH such as PPP, HDLC and
Frame Relay
• Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF
• Performs flag sequence detection and
insertion
• Performs CRC-CCITT and CRC-32
FCS generation and validation
• Performs byte stuffing and destuffing
• Checks for minimum and maximum
packet lengths
• Checks for packet abort sequence
• Performs X⁴³+1 payload scrambling
• Provides a SATURN POS-PHY Level
2 and an 8-bit 100MHz POS-PHY
Level 3 system interface
• Provides synchronous 256 byte
transmit and receive FIFO buffers
PACKAGING
• Implemented in low power 3.3 Volt
CMOS technology
• Packaged in a 304 SBGA
• Industrial temperature range (-40°C to
+85°C)
APPLICATIONS
• WAN and Edge ATM switches
• Multiprotocol switches
• Layer 3 switches
• Routers, Packet switches and Hubs
BLOCK DIAGRAM
TXD+/-
TDREF1,TDREF0
ATP[0]
PTCLK
POUT[7:0]
FPOUT
RBYP
PECLV
REFCLK+/-
RXD+/-
RRCLK+/-
SD
C1,C0
ATP[1]
PICLK
PIN[7:0]
FPIN
OOF
Section/Line
DCC Insert
JTAG Test
Access Port
Tx
Line
I/F
Tx Section
O/H
Processor
Tx Line O/H
Processor
Tx Path O/H
Processor
Section
Trace Buffer
Path Trace
Buffer
WAN
Synch.
Tx POS
Frame
Processor
Tx ATM Cell
Processor
Rx ATM Cell
Processor
Rx
Line
Rx Section
O/H
Processor
Rx Line O/H
Processor
Rx Path O/H
Processor
I/F
Rx POS
Frame
Processor
Section/Line Rx APS, Sync
DCC Extract Status, BERM
Microprocessor
Interfaces
TFCLK
TENB
TCA/TPA
TSOC/TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RENB
RCA/RPA
RSOC/RSOP
RPRTY
RDAT[15:0]
RMOD
REOP
RERR
RVAL
PMC-981280 (R2)
 1999 PMC-Sierra, Inc. January, 1999