PM5352-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – 155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device

PMC-Sierra,Inc.
PM5352
S/UNI®-155-STAR
155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device
FEATURES
• Single channel ATM and Packet-over-
SONET OC-3c (155 Mbit/s) PHY.
• Provides on-chip clock and data
recovery and clock synthesis.
• Exceeds Bellcore-GR-253 jitter
requirements.
• Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
• Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
• Detects signal degrade and signal
failure thresholds crossing alarms.
• Captures and debounces
synchronization status byte (S1).
• Extracts and inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages.
• Extracts and inserts section/line data
communication channels (DCC).
• Provides circuitry to meet holdover,
wander and long term stability.
• Provides a generic 8-bit
microprocessor interface for device
control and register access.
• Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
ATM
• Implements the ATM Forum User
Network Interface Specification.
• Performs cell payload scrambling and
descrambling.
• Provides a UTOPIA Level 2-compliant
system interface.
• Provides synchronous cell transmit
and receive FIFO buffers.
PACKET-OVER-SONET
• Generic design that supports packet-
based protocols like PPP, HDLC and
Frame Relay.
• Implements the PPP over SONET/
SDH specification according to RFC
2615 and 1662 of the IETF.
• Performs flag sequence detection and
insertion.
• Performs CRC-CCITT and CRC-32
FCS generation and validation.
• Performs byte stuffing and destuffing.
• Checks for minimum and maximum
packet lengths.
• Provides a SATURN®-compatible
Packet-over-SONET POS-PHY Level
2 Interface.
PACKAGING
• Low power, 3.3 V CMOS technology.
• Packaged in a 304-pin Ball Grid Array
(BGA) package.
• Industrial temperature range (-40° to
+85°C).
APPLICATIONS
• DSLAM uplinks.
• Access concentrators.
• Layer 3 switches.
• ATM switches.
BLOCK DIAGRAM
TXC+
TXC-
TXD+
TXD-
ATB[3:0]
REFCLK
RXD+
RXD-
SD
CP
CN
Transmit
Line
Interface
Section
DCC
Insert
Line
DCC
Insert
Transmit
Section O/H
Processor
Transmit
Line O/H
Processor
Transmit
Path O/H
Processor
Section Trace
Buffer
Path Trace
Buffer
Receive
Line
Interface
Receive
Section O/H
Processor
Receive
Line O/H
Processor
Section
DCC
Extract
Line
DCC
Extract
Receive
Path O/H
Processor
Receive
APS, Sync,
BERM
JTAG
Test Access
Port
Transmit
ATM Cell
Processor
Transmit
POS Frame
Processor
Receive
POS Frame
Processor
Receive
ATM Cell
Processor
UTOPIA
Level 2 /
POS-PHY
Level 2
System
Interface
Microprocessor
Interface
TMOD
TERR
TEOP
DTCA/DTPA
TDAT[15:0]
TPRTY
TSOC/TSOP
TCA
TADR
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA/DRP
REOP
RERR
RMOD
PMC-991722 (r1) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE© Copyright PMC-Sierra, Inc. 2000