PM5351-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device

PMC-Sierra,Inc.
PM5351
S/UNI-155-TETRA
Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device
FEATURES
• Quad channel ATM and Packet over
SONET OC-3c (155 Mbit/s) PHY.
• Provides on-chip clock and data
recovery and clock synthesis.
• Exceeds Bellcore-GR-253 jitter
requirements.
• Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
• Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
• Detects signal degrade and signal
failure thresholds crossing alarms.
• Captures and debounces
synchronization status byte (S1).
• Extracts and inserts the 16- or 64-byte
section trace (J0) and path trace (J1)
messages.
• Extracts and inserts section/line data
communication channels (DCC).
• Provides circuitry to meet holdover,
wander and long term stability.
• Provides a generic 8-bit
microprocessor interface for device
control and register access.
• Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
ATM
• Implements the ATM Forum User
Network Interface Specification.
• Performs cell payload scrambling and
descrambling.
• Provides a UTOPIA Level 2-compliant
system interface.
• Provides synchronous 4-cell transmit
and receive FIFO buffers.
PACKET OVER SONET
• Generic design that supports packet
based protocols like PPP, HDLC and
Frame Relay.
• Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF.
• Performs flag sequence detection and
insertion.
• Performs CRC-CCITT and CRC-32
FCS generation and validation.
• Performs byte stuffing and destuffing.
• Checks for minimum and maximum
packet lengths.
PACKAGING
• Low power, 3.3 V CMOS technology.
• Packaged in a 304-pin Ball Grid Array
(BGA) package.
• Industrial temp. range (-40° to +85°C).
APPLICATIONS
• WAN and Edge ATM Switches
• Multiprotocol Switches
• Layer 3 Switches
• Routers, Packet Switches, and Hubs
BLOCK DIAGRAM
TXC[4:1]+
TXC[4:1]-
TXD[4:1]+
TXD[4:1]-
ATB[3:0]
REFCLK
RXD[4:1]+
RXD[4:1]-
SD[4:1]
CP[4:1]
CN[4:1]
Transmit
Line
Interface
Receive
Line
Interface
JTAG Test Access Port
Section
DCC
Insert
Line
DCC
Insert
Transmit Section Transmit Line
O/H Processor O/H Processor
Transmit Path
O/H Processor
Section
Trace Buffer
Path Trace
Buffer
Receive Section Receive Line
O/H Processor O/H Processor
Receive Path
O/H Processor
Section
DCC
Extract
Line
DCC
Extract
Receive
APS,
Sync,
BERM
Transmit ATM
Cell Processor
Transmit POS
Frame Processor
Receive POS
Frame Processor
Receive ATM
Cell Processor
Microprocessor Interface
TMOD
TERR
TEOP
DTCA[4:1]/DTPA[4:1]
TDAT[15:0]
TPRTY
TSOC/TSOP
TCA
TADR[4:0]
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR[4:0]
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
PMC-1980862 (R3) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
 2001 PMC-Sierra, Inc.