PM5349-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – Quad 155 Mb/s ATM Physical Layer Device

PMC-Sierra,Inc.
Quad 155 Mb/s ATM Physical Layer Device
PM5349
S/UNI-155-QUAD
FEATURES
• Quad-channel ATM OC-3c
(155 Mb/s) PHY.
• Provides on-chip clock and data
recovery and clock synthesis.
• Exceeds Bellcore-GR-253 jitter
requirements.
• Provides a generic 8-bit
microprocessor interface for device
control and register access.
• Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
SONET RECEIVER
• Recovers clock and data.
• Frames to and descrambles recovered
stream.
• Filters and captures Automatic
Protection Switch (APS) byes (K1, K2)
and detects APS byte failure.
• Detects signal degrade and signal
failure threshold crossing alarms.
• Captures and debounces
synchronization status byte (S1).
• Counts received section BIP-8 (B1),
line BIP-24 (B2), and BIP-8 (B3)
errors, and line and path FEBEs.
• Detects LOS, OOF, LOF, LAIS, LRDI,
LOP, PAIS, PRDI, and PERDI.
• Provides individual divide by eight
recovered clocks for each channel.
• Provides individual 8 kHz receive
frame pulses for each channel.
SONET TRANSMITTER
• Synthesizes the 155.52 MHz transmit
clock from a 19.44 MHz reference.
• Provides a single transmit frame pulse
input to align the transport frames to a
system reference.
• Provides single transmit clock as
timing reference for transmit outputs.
• Inserts register programmable APS
(K1 and K2) and synchronization
status (S1) bytes.
• Inserts PAIS, PRDI, LAIS, and LRDI.
• Scrambles the transmit data stream.
ATM PROCESSOR
• Implements the ATM Forum User
Network Interface Specification.
• Inserts and extracts ATM cells into and
from the SONET SPE.
• Performs cell payload scrambling and
descrambling.
• Provides a UTOPIA Level 2-compliant
system interface.
• Provides synchronous 4-cell transmit
and receive FIFO buffers.
PACKAGING
• Implemented in low power 3.3 V
CMOS technology.
• Packaged in a 304-pin Ball Grid Array
(BGA) package.
• Industrial temp. range (-40° to +85°C).
APPLICATIONS
• Enterprise and Edge ATM Switches
• ATM Switches and Hubs
• Multiprotocol Switches
BLOCK DIAGRAM
TXD[4:1]+
TXD[4:1]-
ATB[3:0]
REFCLK
RXD[4:1]+
RXD[4:1]-
SD[4:1]
Transmit
Line
Interface
Transmit Section Transmit Line
O/H Processor O/H Processor
Transmit Path
O/H Processor
Transmit ATM
Cell Processor
Receive
Line
Interface
Receive Section Receive Line
O/H Processor O/H Processor
Receive
APS,
Sync,
BERM
Receive Path
O/H Processor
Receive ATM
Cell Processor
JTAG Test
Access Port
Microprocessor
Interface
DTCA[4:1]
TDAT[15:0]
TPRTY
TSOC
TCA
TADR[4:0]
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR[4:0]
RCA
RSOC
RPRTY
RDAT[15:0]
DRCA[4:1]
PMC-980863 (R3) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
 1999 PMC-Sierra, Inc.