PM5348 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – SATURN USER NETWORK INTERFACE(155.52 & 51.84 MBIT/S)

PMC-Sierra,Inc.
PM5348
S/UNI-155-DUAL
Two-Channel ATM SATURN User Network Interface
FEATURES
• Provides two independent SATURN^®-
compatible ATM PHY channels in one
chip.
• Provides hardware and software
backward compatibility with the
industry-standard PM5346
S/UNI^®-155-LITE chip.
• Implements the ATM Transmission
Convergence (TC) sublayer according
to ATM Forum specifications using the
SONET/SDH 155.52 Mbit/s STS-3c/
STM-1 and SONET 51.84 Mbit/s
STS-1 formats.
• NRZ data format supports category-5
Unshielded Twisted Pair (UTP-5) or
Shielded Twisted Pair (STP) wiring
and optical datalink modules for fiber
optic cable.
• Includes on-chip clock recovery and
clock synthesis, compliant to Bellcore
and ITU-T requirements.
• Operates in timing master or timing
slave (loop timed LAN) modes.
• Frames to SONET framing bytes (A1,
A2), processes the section and line Bit
Interleaved Parity (B1, B2) and the
Far-End Block Error (Z2) bytes.
• Interprets the H1, H2, and H3 payload
pointer bytes.
• Processes the SONET path overhead
BIP-8 (B3), signal label (C2) and path
status (G1) bytes.
• Allows for protection switching by
monitoring the APS (K1, K2) bytes, bit
error rate thresholds and far-end
synchronization status (S1) bits and
providing interrupts when error
conditions are detected.*
• Inserts and extracts ATM payloads
using ATM cell delineation.
• Provides on-chip 4-cell FIFO buffers in
both transmit and receive paths.
• Operates with a backward compatible
dual 8-bit plus parity or a multi-PHY
compatible 16-bit plus parity*
SATURN-Compliant Interface for
PHYsical layer devices (SCI-PHY™).
• Cell interface is also compatible with
ATM Forum Level 2 UTOPIA direct-
mode specifications.
• Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and monitoring.
• Provides TTL/CMOS compatible inputs
and outputs and differential PECL
inputs.
• Low power, +5 V CMOS technology.
• Packaged in a 28 mm by 28 mm 160-
pin Plastic Quad Flat Pack (PQFP).
*NOTE:Indicates new features not
provided on S/UNI-155-LITE.
APPLICATIONS
• ATM Switches and Hubs
• ATM Routers
• Multichannel ATM Servers
BLOCK DIAGRAM
Line Side
System Side
RXD1+
RXD1-
ALOS1+
ALOS1-
TFP
TXD1+
TXD1-
REFCLK+
REFCLK-
TATP
TXD2+
TXD2-
RXD2+
RXD2-
ALOS2+
ALOS2-
Clock and
Data
Recovery
Serial
to
Parallel
Receive
Framer and
Overhead
Processor
Receive
ATM Cell
Processor
Receive
ATM
4-Cell
FIFO
Driver
Clock
Generator
Driver
Clock and
Data
Recovery
Analog Edge
Parallel
to
Serial
Parallel
to
Serial
Serial
to
Parallel
Transmit
Framer and
Overhead
Processor
Transmit
Framer and
Overhead
Processor
Transmit
ATM Cell
Processor
Transmit
ATM Cell
Processor
Transmit
ATM
4-Cell
FIFO
Transmit
ATM
4-Cell
FIFO
Receive
Framer and
Overhead
Processor
Receive
ATM Cell
Processor
Receive
ATM
4-Cell
FIFO
Output Port
Microprocessor
Interface
SCI-PHY
Interface
TSOC[2:1]
TXPRTY[1:0]
TDAT[15:0]
TCA[2:1]
TWRENB[2:1]
TFCLK
RSOC[2:1]
RXPRTY[1:0]
RDAT[15:0]
RCA[2:1]
RRDENB[2:1]
RFCLK
TSEN
JTAG
PMC-950446 (R4)
© 1998 PMC-Sierra, Inc. October, 1998