PM5346 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – S/UNI-LITE ERRATA NOTICE

PMC-Sierra,Inc.
PM5346
S/UNI-155-LITE
155 Mb/s SATURN User Network Interface for LANs
FEATURES
• Low-cost, monolithic SATURN^®
SONET/SDH ATM User Network
Interface (UNI).
• Implements the ATM transmission
convergence (TC) sublayer according
to ATM Forum specifications using the
SONET/SDH 155.52 Mbit/s STS- 3c/
STM-1, and 51.84 Mbit/s STS-1
formats.
• Supports ATM-Forum mid-range PHY
and PMC-Sierra UNI-PHY™ subrates
at 25.92 and 12.96 Mbit/s.
• Supports UTP-5 or STP twisted pair
wiring interface devices and optical
driver and receiver modules for fiber
optic cable interfaces.
• Includes on-chip, Bellcore-compliant
clock recovery and clock synthesis.
• Operates in timing master or timing
slave (loop timed) modes.
• Frames to SONET/SDH framing bytes
(A1 and A2), processes the section
and line Bit Interleaved Parity (B1 and
B2) and the Far-End Block Error (Z2)
bytes.
• Interprets the H1, H2, and H3 payload
pointer bytes.
• Processes the SONET path overhead
BIP-8 (B3), signal label (C2), and path
status (G1) bytes.
• Inserts and extracts ATM payloads
using ATM cell delineation.
• Provides on-chip FIFO buffers in both
transmit and receive paths.
• Provides on-chip support for Generic
Flow Control (GFC) and XOFF flow
control.
• Provides a synchronous, 8-bit, plus-
parity SATURN-Compliant Interface for
PHYsical layer devices (SCI-PHY™)
bus operating at 33 MHz.
• Compatible with ATM Forum UTOPIA
interface format, with support for multi-
PHY applications.
• Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and monitoring.
• Provides TTL-compatible inputs and
outputs and differential PECL inputs.
• Low power, +5 V CMOS technology.
• Packaged in a 128-pin 14 mm by
20 mm Plastic Quad Flat Pack (PQFP)
with 0.5 mm lead pitch.
APPLICATIONS
• 155.52, 51.84, 25.92 and 12.96 Mbit/s
Twisted Pair or Optical ATM LANs
• Workstations and Personal Computer
NIC Cards
• Switches, Hubs, and Router Port
Cards
• SONET- or SDH-Compliant ATM UNIs
BLOCK DIAGRAM
Line Side
System Side
TRCLK+
TRCLK-
TXC+
TXC-
TXD+
TXD-
RXDO+
RXD+
RXD-
RXDO-
RRCLK+
RRCLK-
ALOS+
ALOS-
Clock
Generator
Driver
Parallel
to Serial
Data
Recovery
Clock
Recovery
Serial to
Parallel
Transmit
Framer and
Overhead
Processor
Receive
Framer and
Overhead
Processor
Transmit ATM
Cell
Processor
Transmit ATM
Cell FIFO
Receive ATM
Cell
Processor
Receive ATM
Cell FIFO
Microprocessor
Interface
TSOC
TXPRTY
TDAT[7:0]
TCA
TWRENB
TFCLK
RSOC
RXPRTY
RDAT[7:0]
RCA
RRDENB
RFCLK
TSEN
PMC-930908 (R9) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1998 PMC-Sierra, Inc. October,