PM5315 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s

PMC-Sierra,Inc.
Preliminary
PM5315
SPECTRA-2488
SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s
FEATURES
• Monolithic SONET/SDH Payload
Extractor/Aligner for use in interface
applications, operating at serial
interface speeds of up to 2488 Mbit/s:
• single STS-48c (STM-16/AU4-16c);
• single STS-48 (STM-16/AU4-
4c/AU4/AU3/TU3);
• quad STS-12c (STM-4/AU4-4c);
• quad STS-12 (STM-
4/AU4/AU3/TU3).
• In single STS-48/STM-16 mode,
supports a duplex 16-bit 155.52 MHz
differential PECL line side interface for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
• In quad STS-12/STM-4 mode,
supports four duplex 8-bit 77.76 MHz
TTL compatible line side interfaces for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
• Provides termination for SONET
Section, Line and Path overhead or
SDH Regenerator Section, Multiplexer
Section and High Order Path
overhead.
• In single STS-48/STM-16 mode
provides a 32-bit 77.76 MHz ADD and
DROP TelecomBus.
• In quad STS-12/STM-4 mode provides
four 8-bit 77.76 MHz ADD and DROP
TelecomBus Interfaces.
• Maps SONET/SDH payloads to
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
• The entire SONET/SDH transport and
path overheads are extracted to and
inserted from dedicated pins.
• Frames to the SONET/SDH receive
stream and inserts framing bytes and
STS identification into the transmit
stream and processes or inserts the
transport overhead.
• Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
• Provides Time Slot Interchange (TSI)
function at the ADD and DROP
TelecomBus Interfaces for grooming
any legal mix of SONET/SDH paths.
• Supports Automatic Protection
Switching (APS):
• Ring control port communication of
path REI and path RDI alarms;
• Filters the APS channel (K1,K2)
bytes into internal registers; inserts
the APS channel into the transmit
stream.
• Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
an ADD TelecomBus interface to a
DROP TelecomBus interface.
• Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
BLOCK DIAGRAM
Status
Information
Receive O/H Clock,
Frame Pulse
Receive Transport
Overhead
Receive Section/Line
DCC and Clock
Receive Path
Overhead
Bit-interleaved
Parity Error
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
Rx Ring
Control
Port
Rx Line
Interface
Tx Line
Interface
Rx APS
Sync
Extractor
&
Bit Error
Monitor
Section
Trace
Processor
RX Transport
O/H Processor
SONET/SDH
Alarm
Reporting
Controller
Section
Trace
Processor
Tx Transport
O/H Processor
Tx Ring
Control Port
Path
Trace
Processor
(STS-12) Receive Path Processing Slice
Rx Path O/H
Processor
Rx
Telecom
Aligner
Drop Bus
PRBS
Generator/
Monitor
Path
Trace
Processor
(STS-12) Transmit Path Processing Slice
Tx Path O/H
Processor
Tx
Telecom
Aligner
Add Bus Tx Pointer
PRBS Interpreter
Generator/ (STS/AU-
Monitor
TU3)
JTAG Test
Access Port
Mode
Rx Timeslot
Interchange
Rx
TelecomBus
System
Interface
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Alarm
Reporting
Tx
TelecomBus
System
Interface
Tx Timeslot
Interchange
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Microprocessor Interface
PMC-2000326 (p1)
Transmit O/H Control
Clock, Frame and
Pulse
Status
Transmit Information
Section/Line
DCC Clock
Transmit
Transport
O/H
Transmit Path
O/H
Test Data
Quad 622
or 2488
16-bit
Microprocessor
Bus
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2000