PM5313-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces

PMC-Sierra,Inc.
PM5313
SPECTRA-622
SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces
FEATURES
The SPECTRA-622 chip offers the
following features:
• Monolithic SONET/SDH
Payload-Extractor/Aligner for use in
STS-12 (STM-4/AU3 or STM-4/AU4) or
STM-12c (STM-4/AU4-4c) interface
applications that operate at serial
interface speeds up to 622.08 Mbit/s.
• Provides integrated clock recovery and
clock synthesis to allow a direct interface
to optical modules.
• Complies with Bellcore GR-253-CORE
jitter tolerance and intrinsic jitter criteria.
• Provides control circuitry required to
comply with WAN clocking requirements
for wander, holdover, and long term
stability.
• Provides termination for SONET Section
and Line, and SDH Regenerator Section
and Multiplexer Section
transport-overhead. Also provides
termination for Path overhead of twelve
STS-1 (STM-0/AU3) paths, four STS-3/
3c (STM-1/AU3/AU4) paths, or a single
STS-12c (STM-4/AU4-4c) path.
• Maps twelve STS-1 (STM-0/AU3)
payloads, four STS-3/3c (STM-1/AU3/
AU4) payloads, or a single STS-12c
(STM-4/AU4-4c) payload to system
timing references. This accommodates
plesiochronous timing offsets between
the references.
• Maps twelve DS3 bit-streams into an
STS-12 (STM-4/AU3) frame.
• Configurable on an STS-1 basis to
support a mix of traffic from the DS-3 and
Telecom interfaces.
• Provides a Time-Slot Interchange (TSI)
function on the Telecom Add and Drop
buses for grooming twelve STS-1
(STM-0/AU3) paths or four STS-3/3c
(STM-1/AU3/AU4) paths.
• Supports line loopback and diagnostic
loopback.
• Supports OC-48 (STM-16) applications
with byte interfaces for connection to
an OC-48 front-end device.
• Supports diagnostic 2²³-1
pseudo-random bit-sequence (PRBS)
generation and monitoring.
• Provides a standard JTAG test-port for
boundary scan board-test purposes.
• Provides a generic 8-bit
microprocessor bus-interface.
• Low-power 3.3V CMOS with TTL
compatible inputs and CMOS/TTL
digital outputs. PECL inputs and
outputs are 3.3V and 5V compatible.
• Available in a 520-pin SBGA package.
• Supports industrial temperature-range
(-40°C to 85°C) operation.
BLOCK
DIAGRAM
TCLK/PGMTCLK
/TFP
TC1J1V1/TFPO
TFPI
TDCK
TXD+/-
TPL
TD[7:0]
TDP
TDREF/ TDREF1
PECLV
REFCLK+/-
RXD+/-
RRCLK+/-
SD
C0, C1
PICLK
PIN[7:0]
FPIN
OOF
ATP[1:0]
PREFEN
PECLREF
RCLK/PGMRCLK
/RFP
Tx Ring
Control Port
Tx Transport O/H
Controller
Rx Ring
Control Port
Rx Transport O/H
Controller
Transmit Path Processing Slice x12
DS3 Mapper
Add Side
Serial
Control Port
Tx Path O/H
Processor
Receive Path Processing Slice x12
Path Trace Buffer
Rx Telecom
Aligner
Drop Bus PRBS
Generator/
Monitor
Rx Path O/H
Processor
DS3 Mapper
Drop Side
Microprocessor Interface
JTAG Test
Access Port
TPAISCK
TPAISFP
TPAIS
DS3TICLK [12:1]
DS3TDAT [12:1]
AC1J1V1[4:1]/
AFP[4:1]
ACK
APL[4:1]
AD[31:0]
ADP[4:1]
DMODE[1:0]
DCK
DC1J1V1[4:1]
DPL[4:1]
DD[31:0]
DDP[4:1]
DFP
DS3ROCLK [12:1]
DS3RICLK
DS3RDAT [12:1]
DPAISCK
DPAISFP
DPAIS
PMC-1981271 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT’S CUSTOMERS’ INTERNAL USE  2001 PMC-Sierra, Inc.