PM3386-1 Datasheet, PDF (1/2 Pages) PMC-Sierra, Inc – Dual Gigabit Ethernet Controller

Dual Gigabit Ethernet Controller
PM3386
S/UNI®-2xGE
FEATURES
• Two port full-duplex Gigabit Ethernet
Controller with an industry standard
POS-PHY Level 3™ system interface.
• Provides direct connection to optics.
• Connection to copper Gigabit Ethernet
physical layer devices via two GMII
interfaces.
• Incorporates dual SERDES,
compatible to IEEE 802.3 1998 PMA
physical layer specification.
• Supports dual IEEE 802.3 -1998
GMII/TBI interfaces for connection to
copper Gigabit Ethernet physical layer
devices.
• Provides dual standard IEEE 802.3
Gigabit Ethernet MACs for frame
verification.
• Provides on-chip data recovery and
clock synthesis.
• Provides eight unicast exact-match
address filters to filter frames based on
DA, SA, or VID.
• Each address filter can indicate
whether to accept or discard based on
a match.
• Provides 64-group multicast address
filter.
• Internal 16 kbyte TX and 64 kbyte RX
FIFOs to accommodate system
latencies.
• SATURN® compatible interface for
Packet-Over-SONET Physical Layer
and Link Layer devices Level 3 (POS-
PHY Level 3 system interface).
• Line side loopback for system level
diagnostic capability.
• 16 bit generic microprocessor interface
for device initialization, control, register
and per port statistics access.
GIGABIT ETHERNET MAC
• Verifies frame integrity (FCS and
length checks).
• Errored frames can be filtered or
passed to a higher layer device.
• Automatic Base Page Autonegotiation,
extended Autonegotiation (Next Page)
supported via host.
• Egress Ethernet frame encapsulation
(pad to minimum size, add preamble,
IFG and CRC generation).
• Supports Ethernet 2.0, IEEE 802.3 LLC
and IEEE 802.3 SNAP/LLC encoding
formats, and VLAN tagged frames.
• Minimum frame size 64 bytes. Supports
jumbo frames up to 9.6 kbytes.
• Supports big endian data formats.
• Programmable inter-packet gap (IPG).
• Loopback for diagnostic capability
through GMAC.
FLOW CONTROL
• Option to support IEEE 802.3-1998
flow control at each Ethernet port.
• Programmable watermarks for
full/empty FIFO conditions.
• Automatic generation of pause frames
based on FIFO fill levels.
• Upper layer device can flow control
Ethernet ports using side-band or host
signaling to cause generation of a
Pause frame.
• Provides per-port side-band Pause
state indication for upstream devices.
• Loss-less flow control on all valid
frames up to 9.6 kbytes.
STATISTICS
• 40 bit counters are used to ensure
rollover compliance with
IEEE 802.3-1998.
• Minimum 58 minutes before rollover.
• Provides statistic counters to support
SNMP and RMON implementations.
POS-PHY LEVEL 3 SYSTEM
INTERFACE
• Standard OC-48 bandwidth
Packet/Cell interface.
• Compatible with PMC-Sierra devices
supporting POS-PHY Level 3, including:
• PM5381 S/UNI®-2488 ATM and
POS physical layer device.
• PM5358 S/UNI®-4x622 single
channel OC-48c device with
integrated analog.
• PM7390 S/UNI-MACH-48 multi-
service access device for
channelized interfaces.
• PM5382 S/UNI-16x155 sixteen
channel OC-3c framer with
integrated analog and POS-PHY
Level 3 and UTOPIA Level 3
interface.
• POS-PHY Level 3 provides connection
to upper layer device at data rates up
to 2,400 Mbit/s.
BLOCK DIAGRAM
MDC
MDIO
RX_CLK
RX_DV
RX_ER
RXD [7:0]
GTX_CLK
TX_EN
TX_ER
TXD [7:0]
RXD +/-
SD
CLK125
TXD +/-
ATP[3:0]
Ethernet Statistics
Enhanced Gigabit MAC
GMII
Interface
Flow Ctrl /
Auto-Negotiation
Address
Filtering
Data Recovery/
Serial to Parallel
PLL Clock
Multiply
Parallel to Serial
SERDES
Microprocessor
Interface
8B/10B
Encoder/
Decoder
Gigabit
Media
Access
Controller
PCS
MAC
JTAG
POS-PHY
Level 3
Ingress
Interface
POS
PHY
Ingress
FIFO
Egress
Interface
POS
PHY
Egress
FIFO
PAUSE [1:0]
PAUSED [1:0]
RFCLK
RENB
RDAT[31:0]
RMOD[1:0]
RPRTY
RVAL
RSOP
REOP
RERR
RSX
DTPA[1:0]
STPA
PTPA
TADR
TFCLK
TENB
TDAT[31:0]
TMOD[1:0]
TPRTY
TSOP
TEOP
TERR
TSX
PMC-1991223 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001