PCI9656 Datasheet, PDF (1/4 Pages) PLX Technology – 64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC™ & Generic 32-bit, 66MHz Local Bus Designs

VERSION 1.0 2002
Connectivity
s 64-bit, 66MHz PCI r2.2 compliant
s Motorola PowerQUICC and
generic 32-bit, 66MHz local
bus modes
s 3.3V I/O, 5V tolerant bus
interfaces
s PICMG 2.1 r2.0 Hot Swap Silicon
s 272-ball, 27 x 27 mm, 1.27 mm
pitch PBGA
Performance
s Zero wait state burst operation
– PCI bus bursts to 528 MB/sec
– Local bus bursts to 264 MB/sec
s 2 DMA Channels
– Block and Scatter/Gather transfers
– DMA descriptor ring management
– Demand Mode and EOT
Hardware controls
s Direct Master data transfers
– Generate any PCI transaction
– Read ahead and programmable
read prefetch counter
s Direct Slave data transfers
– Access 8-, 16-, and 32-bit local
bus devices
– Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
Control
s I2O r1.5 messaging unit
s Eight mailbox and two
doorbell registers
s PCI arbiter supports 7
external masters
s Host mode reset/interrupt signal
configuration
s PCI D3_COLD Power Management
Event (PME) generation support
s Serial EEPROM interface
s JTAG boundary scan
PCI 9656
64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
PowerQUICC^™ & Generic 32-bit, 66MHz Local Bus Designs
Maximum PCI Bandwidth for Your 32-bit Local Bus Applications
The PCI 9656 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
Motorola^® MPC 850/860 PowerQUICC Designs
The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection
to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its
Data Pipe Architecture™ technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-
ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.
The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI
I/O with those devices.
Move Your 32-bit Local Bus Designs Up to
64-bit, 66MHz PCI Operation
As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX
continues to provide leading edge, high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of
enhancements for the needs of today's telecom, networking, and I/O adapter designs:
s 64-bit, 66MHz PCI operation
s 32-bit, 66MHz local bus operation
s Dynamic DMA descriptor ring management with Valid bit semaphore control
s PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit
Initialization, and Intially Not Responding Support
s PCI Power Management r1.1 D3_COLD Power Management Event (PME) generation
s PCI arbiter supporting 7 external masters
s Reset and interrupt pins configurable for embedded host applications
s JTAG boundary scan
The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.