PL612-05 Datasheet, PDF (3/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC

(Preliminary)
1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC
FUNCTIONAL DESCRIPTION
The PL612-05 is a highly featured, very flexible, advanced Dual PLL design for high performance, low-power
applications. Starting from a low-cost fundamental input crystal of 10MHz to 50MHz or a reference clock input of
1MHz to 200MHz, the PL612 is capable of producing 3 (SOP-8L) or 5 (MSOP-10L) distinct output frequencies of up
to 200MHz. Both PLLs are fully programmable, with a total of three Odd/Even (patent pending) ‘5-bit’ Post VCO
(P-counter) dividers with additional 1, 2, 4 or 8 ‘Post P-counter’ dividers to allow generating the most demanding
frequencies easily. The outputs can be programmed to deliver the generated frequencies from the PLLs, or the
reference input. Each bidirectional feature pin (I/O) on the PL613-05 incorporates a 60KΩ pull up resistor (10MΩ
for PDB function) and can be configured to perform various functions. Usage of various design features of these
products is mentioned in the following paragraphs.
PLL Programming
OEM (Master Output Enable)
The two PLLs in PL612-05 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The PLL outputs
are transferred to Odd/Even (patent pending) 5-bit
post VCO dividers (P-Counter), as shown in the
above diagrams. In addition, there are three optional
(÷1, ÷2, ÷4 or ÷8) ‘post P-Counter’ dividers that can
further divide the VCO frequency. In general, the
PLL output frequency is determined by the following
formula
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of the
PL612-05. In addition the state of the disabled outputs
can be programmed to float (Hi Z) or to operate in the
‘Active low’ mode. The OEM Function operates on the
following logic:
OEM
OE Type
Osc PLL Output
Pin (Programmable)
0 (Default)
On On Hi Z
0
1
On On Active ‘0’
FOUT = (FREF *M) / (R*P).
For output calculations, please note that ‘P’ includes
the ‘P’ counter bits plus the additional optional (÷1,
÷2, ÷4 or ÷8) dividers, if used.
CLKx (Clock Outputs)
There are a maximum of 3 (SOP-8L) or 5 (MSOP-
10L) outputs available on the PL612-05. Clock output
frequencies can be configured as follows:
CLK[0]
FVCO2 / P
CLK[1]
FVCO1 / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[2]
FREF / (P*(1,2,4,8))
CLK[3]
FVCO2 / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[4]
FREF / P
1
Normal Operation (Default)
Note: Typical enable time is 10ns.
Power-Down Control (PDB)
When activated, PDB ‘Disables all the PLLs, the
oscillator circuitry, counters, and all other active
circuitry. PDB activation disables all outputs and the
IC consumes <10µA of power. The PDB input
incorporates a 10MΩ pull up resistor for normal
operating condition.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The logic for PDB is shown below:
PDB PDB Type
Osc PLL
Pin Program
Output
Hi Z
0
Off Off
0
(Default)
1
Off Off Active ‘0’
1
Normal Operation (Default)
Note: Typical enable time is 2ms.
Each output can be programmed with a 4mA, 8mA, or
16mA drive strength. The maximum output frequency
is 200MHz @ 3.3V, 166MHz @ 2.5V or 133MHz @
1.8V.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 9/4/07 Page 3