PLL701-13 Datasheet, PDF (2/5 Pages) PhaseLink Corporation – Low EMI Spread Spectrum Multiplier Clock

BLOCK DIAGRAM
PLL701-13
Low EMI Spread Spectrum Multiplier Clock
FIN
S(0:3)
PLL
SST
Control
Logic
FOUT
PIN DESCRIPTIONS
Name
FIN
S2
S1
S0
GND
FOUT
Number
1
2
3
4
5
6
S3
7
VDD
8
Type
I
I
I
I
P
O
I
P
Description
Input Clock Frequency, 24MHz to 120MHz.
Digital control input to select multiplication factor and SST modulation
amplitude. Has internal pull-up.
Digital control input to select multiplication factor and SST modulation
amplitude. Has internal pull-up.
Digital control input to select multiplication factor and SST modulation
amplitude. Has internal pull-down.
Ground.
SST Modulated Clock Frequency Output. The frequency before modulation is
synthesized by multiplying the input frequency by 1X, 2X, or 4X, depending on
S(0:3).
Digital control input to select multiplication factor and SST modulation
amplitude. Has internal pull-down.
3.3V Power Supply.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 08/12/04 Page 2