PLL502-14 Datasheet, PDF (2/6 Pages) PhaseLink Corporation – 192MHz - 400MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystal)

Preliminary PLL502-14
192MHz – 400MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystal)
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
VIN
GND
GND_BUF
CLK
VDD_BUF
CLKB
Number
1,2,16
3
4
5
6
7,8,9,10
11,15
12
13
14
Type
Description
P +3.3V Power supply connectors.
I Crystal input pin.
I Crystal output pin.
I
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
I Frequency control voltage input pin.
P GND Power connectors.
P GND connector for output buffers.
O True clock output pin.
P +3.3V Power supply connector for output buffers.
O Complementary clock output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
VDD
7
V
VI
VSS-0.5 VDD+0.5
V
VO
VSS-0.5 VDD+0.5
V
TS
-65
150
°C
TA
-40
85
°C
TJ
125
°C
260
°C
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
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Rev 7/15/02 Page 2