PL613-05 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoTreoTM, 3-PLL, 200MHz, 5 Output Clock IC

(Preliminary)
1.8V-3.3V PicoTreo^TM, 3-PLL, 200MHz, 5 Output Clock IC
PIN CONFIGURATION
XIN/FIN 1
8
CLK2/OEM^/PDB^ 2
7
VDD 3
6
CLK0 4
5
SOP-8L
PACKAGE PIN ASSIGNMENT
XOUT
VDD
CLK1
GND
GND
CLK4/CSEL^
CLK2/OEM^/PDB^
VDD
CLK3
^ Denotes internal pull up
1
10
2
9
3
8
4
7
5
6
MSOP-10L
XIN/FIN
XOUT
VDD
CLK1
CLK0
Name
Package Pin #
Type
MSOP-10L SOP-8L
Description
GND
1
5
P GND connection
CLK4/CSEL
- Programmable Clock (CLK4) output or
2
-
B*
- Configuration Switching input
CLK2/OEM/PDB
3
- Programmable Clock (CLK2) output, or
2
B* - Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
VDD
4, 8
3, 7
P VDD connection
CLK3
5
-
O Programmable Clock (CLK3) output
CLK0
6
4
B* Programmable Clock (CLK0) output
CLK1
7
6
O Programmable Clock (CLK1) output
XOUT
9
8
O Crystal output pin. Do Not Connect when using FIN
XIN/FIN
10
1
I Crystal or Reference Clock input
* Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:4 ]
Output Frequency
CLK[0]
FVCO2 / P
CLK[1,2]
FVCOx / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[3]
FVCO2 / (P*(1,2,4,8)) or FREF / (P*(1,2,4,8))
CLK[4]
FVCO3 / P or FREF / P
Where FVCO = FREF * M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
Output Drive Strength
Each output has
three optional drive
strengths to choose
from. They are:
 Low: 4mA
 Std: 8mA (default)
 High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
 OEM – (Master OE controlling all outputs)
 CSEL – (Device Configuration Switching)
 PDB – (Power Down)
 CLK[0:4] – (Output)
 HiZ or Active Low disabled state
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 7/2/07 Page 2