PL611S-27 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 1.8V to 3.3V PicoPLLTM Programmable Clock

P (Preliminary) L611s-27
1.8V to 3.3V PicoPLL^TM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
• OE - input
• PDB - input
• FSEL – input
• HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
CLK1
GND
FIN
Pin Assignment
DFN SOT
Pin# Pin #
2
1
3
2
1
3
Type
O
P
I
Description
Programmable Clock Output
GND connection
Reference input pin
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down (PDB) input or Frequency Switching (FSEL) input. This
pin has an internal 60KΩ pull up resistor.
OE,
PDB,
6
4
The OE and PDB features can be programmed to allow the output to float
I
(Hi Z), or to operate in the ‘Active low’ mode.
FSEL
State
OE
PDB
FSEL
0
Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode
Frequency ‘1’
VDD
5
5
P
VDD connection
CLK0
4
6
O Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
PDB
Osc.
PLL
CLK0
CLK1
1
N/A
On
On
0
N/A
On
Off
N/A
1
On
On
N/A
0
Off
Off
On
HiZ or Active Low
On
HiZ or Active Low
On
On
On
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 2/25/07 Page 2