PL611S-19 Datasheet, PDF (2/8 Pages) PhaseLink Corporation – 0.5kHz-55MHz MHz to KHz Programmable ClockTM

P (Preliminary) L611s-19
0.5kHz-55MHz MHz to KHz Programmable Clock^TM
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 8 bit
R = 5 bit
P = 14 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
PIN CONFIGURATION AND DESCRIPTION
Programmable
Input/Output
One output pin can be configured as:
• OE - input
• FSEL - input
• PDB – input
• HiZ or Active Low disabled state
FIN 1
CLK1 2
GND 3
6 OE, PDB, FSEL
CLK1 ₁
5 VDD
4 CLK0
OE, PDB, FSEL ₂
6 ^CLK0
5 ^GND
FIN _{3 4} VDD
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-6L
(2.3mmx2.25mmx1.0mm)
CLK1 1
GND 2
FIN 3
6 CLK0
5 VDD
4 OE, PDB, FSEL
SOT23-6L
(3.0mmx3.0mmx1.35mm)
Name
CLK1
GND
FIN
OE, PDB,
FSEL
VDD
CLK0
Pin Assignment
DFN SC70 SOT
Pin# Pin# Pin #
2
1
1
3
5
2
1
3
3
6
2
4
5
4
5
4
6
6
Type
Description
I/O Programmable Clock Output
P GND connection
I Reference input pin
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or On-the-Fly Frequency Switching
Selector (FSEL). This pin has an internal 60KΩ pull up resistor for OE,
O _{PDB & FSEL.}
The OE and PDB features can be programmed to allow the output to float
(Hi Z), or to operate in the ‘Active low’ mode.
P VDD connection
O Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
PDB
Osc.
PLL
CLK0
1
N/A
On
On
On
0
N/A
On
Off
HiZ or Active Low
N/A
1
On
On
On
N/A
0
Off
Off
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
CLK1
On
On
On
HiZ or Active Low
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/12/06 Page 2