PL560-08 Datasheet, PDF (2/15 Pages) PhaseLink Corporation – Analog Frequency Multiplier

Analog Frequency Multiplier
VCXO Family of Products
VCon
L2X
X IN
XOUT
O scilla to r
A m p lifie r
O n ly re q u ire d in x4 d e sig n s
F re q u e n c y
X2
F re q u e n c y
X4
L4X
Figure 2: Overall VCXO AFM Block Diagram
OECTRL
QBAR
Q
Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low
rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonic below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
PECL
LVDS or CMOS
0 (Default)
1
0 (Default)
1
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
47745 Fremont Blvd., Fremont, CA 94538 TEL [phone], FAX [phone] www.phaselink.com Rev.:03-22-05 Page 2