TB502-02 Datasheet, PDF (1/1 Pages) PhaseLink Corporation – Layout Recommendation and Test Board for PLL502-02

TB502-02
Layout Recommendation and Test Board for PLL502-02
This note provides Layout recommendations for the PLL502-02 and documents the test
board prepared for the PLL502-02
Best phase noise and jitter performance is achieved by applying good decoupling practices between VDD and GND, and best pull-range
performance is obtained by optimizing the layout in order to minimize parasitic capacitances on the board.
As an example, and to simplify testing and evaluation of PLL502-02 by customers, PhaseLink provides a test board that implements the
best approaches for decoupling the VCXO chip using discrete external components. It is brought to the attention of our customers that
PLL502-02 is pin-to-pin compatible with PLL501-01 and PLL501-05, with the exception of pin#2 which is not connected internally on
PLL502-02.
While this test board achieves satisfactory decoupling results, best results are achieved when the VCXO chip is laid out into the final
PCB, following the recommendations indicated in the data sheet.
1. External Components and Layout Recommendations (as per PLL502-02 data sheet)
The PLL502-02 requires a minimum number of external components for proper operation. A standard low frequency decoupling
capacitor of 4.7µF or more should be used between VDD (pin 6) and GND. Additionally, higher frequency decoupling capacitors of
0.1µF are required between VDD and GND. These higher frequency decoupling capacitors must be connected as close to the PLL502-
02 chip as possible, and preferably directly next to the PLL502-02 pins. A series termination resistor of 33Ω may be used for the clock
output (series termination resistor not implemented on test board).
The input crystal must be connected as close to the chip as possible, and preferably directly next to the PLL502-02 pins. Care must be
given to the CL rating of the crystal: at nominal voltage control (1.65V) the load capacitance presented to the crystal by the PLL502-02
is 9.5pF. Therefore, if a crystal with CL higher than 9.5pF is used, it will require additional (fixed) loading capacitors externally to
complement the internal 9.5pF of the PLL502-02: one between each crystal electrode and GND, as close to the crystal as possible, and
preferably directly next to the crystal electrodes. Example, for crystal rated for CL = 14.5pF, two external 10pF capacitors (one between
each electrode of the crystal and GND) are required in order to load the crystal correctly. The two external capacitors (seen in series by
the crystal) result in an additional 5pF in parallel to the 9.5pF presented by the PLL502-02, thus providing the total 14.5pF required by
the crystal (9.5pF // 5pF = 14.5pF). However, if the crystal used with the PLL502-02 is rated for a CL = 9.5pF, no external capacitors
are requiredConsult PhaseLink for recommended suppliers.
2. Crystal Specifications (as per PLL502-02 data sheet)
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
Crystal Pullability
Recommended ESR
SYMBOL
FXIN
CL (xtal)
C0/C1 (xtal)
RE
CONDITIONS
Parallel Fundamental Mode
At VIN = 1.65V
AT cut
AT cut
MIN. TYP. MAX. UNITS
10
20
MHz
9.5
pF
250
-
30
Ω
3. Test board schematic
+3.3V
XTAL, NSK 17.664 MHz, 14 pF
Note: C5 and C4
are only
required if
a crystal of
CL greater
than 9.5 pF
is used.
Please order a
test board without
external C5 and
C4 capacitors if
you intend to use
a crystal of CL
equal to 9.5pF.
C3
4.7 uf
Vin control
R1 = 0Ω
?
R1= 0 or 10
C6
0.1uf
C1
0.1uf
17.664 MHz
Y1
C5
C4
10 pF 10 pF
U1
1
2
3
XIN XOUT
VDD GND
8
7
6
4
CTRL VDD
GND CLK
5
PPLLLL550021--0021
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Clock output
C2
0.1uf
Rev 10/30/01 Page 1