PLL702-01 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – Clock Generator for PowerPC Based Applications

PLL702-01
Clock Generator for PowerPC Based Applications
FEATURES
• 1 CPU Clock output with selectable frequencies (50,
66, 75, 80, 83, 90, 100,125 or 133 MHz).
• 1 ASIC output clock (at CPU clock or CPU clock ÷ 2).
• 2 ASIC output clocks (at CPU clock) w/ output enable.
• 1 PCI output clock w/ output enable
• 1 Selectable 48, 30 or 12MHz (USB) output.
• Selectable Spread Spectrum (SST) for EMI reduction
on ASIC and CPU.
• PowerPC compatible output and drive CPU Clock.
• Selectable reduced 67% drive strength on CPU Clock
• Advanced, low power, sub-micron CMOS processes.
• 14.31818MHz fundamental crystal input.
• 3.3V and/or 2.5V operation.
• Available in 28-Pin 209mil SSOP (QSOP).
DESCRIPTION
The PLL702-01 is a low cost, low jitter, and high
performance clock synthesizer for generic PowerPC based
applications. It provides one CPU clock, three ASIC
outputs, one PCI output, and a selectable 48, 30 or 12MHz
(USB) output. The user can choose between 9 different
CPU clock frequencies, while the ASIC output can be
identical or half of the CPU frequency. Low EMI Spread
Spectrum Technology is available for the CPU, ASIC and
PCI clocks. The CPU drive strength is user selectable from
100% to 67%. All frequencies are generated from a single
low cost 14.31818MHz crystal. The CPU and ASIC clock
can be driven from an independent 2.5V power supply.
BLOCK DIAGRAM
PIN ASSIGNMENT (28 pin SSOP)
CPUDRV_SEL^
1
XIN
2
XOUT / ASIC2_OE*^ 3
VDD_ANA 4
VDD_DIG
5
VDD_PC I
6
PCI / PCI_SEL*T
7
GND_PCI
8
GND_USB 9
VDD_USB 10
USB / USB_SEL*^T 11
VDD_ASIC2 12
ASIC2 A 13
ASIC2 B 14
Note : ^{^: Internal pull-up resistor}
o_{: Selectable reduced drive}
strength
28
CLK_SEL0^T
27
CLK_SEL1T
26 SSCO^{^}
25 SSC1^{^}
24 GND_ANA
23 GND_CPU
22
CP U ^o
21 VDD_CPU
20 VDD_ASIC1
19 ASIC1
18 GND_ASIC1
17 _{ASIC1_SEL^}
16 GND_DIG
15 GND_ASIC2
*: Bi-directional pin
T_{: Tri-level input}
FREQUENCY TABLES
CLK_SEL1
CLK_SEL0
CPU
(MHz)
0
0
50
ASIC1 (MHz)
ASIC1_SEL
=1
ASIC1_SEL
=0
50
25
ASIC2
(MHz)
50
PCI* (MHz)
PCI_SEL PCI_SEL
=0
=M
62.5 31.25
0
M
66
66
33
66 66.7 33.35
0
1
75
75
37.5
75 62.5 31.25
M
0
80
80
40
80 66.7 33.35
M
M
83
83
41.5
83 66.7 33.35
M
1
90
90
45
90 66.7 33.35
1
0
100
100
50
100 66.7 33.35
1
M
125
125
62.5
125 62.5 31.25
1
1
133
133
66.5
133 65.5 32.75
Notes: When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When
CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.
* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.
USB_SEL
Control
Logic
PLL
USB
CPU_CLK
XIN
XOUT
SSC(0:1)
CLK_SEL(0:1)
ASIC1_SEL
PCI_SEL
XTAL
OSC
PLL
DIV 2
SST
ASIC2_OE
Control
Logic
PCI_OE
ASIC1
ASIC2(A:B)
PCI
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 07/18/05 Page 1