PLL701-50 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – Low EMI Spread Spectrum Multiplier IC

PLL701-50
Low EMI Spread Spectrum Multiplier IC
FEATURES
• Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
• 13MHz to 224MHz output with output enable.
• 13MHz to 30 MHz input frequency from crystal or
external clock signal.
• Reduced EMI from Spread Spectrum Modulation,
with selectable modulation magnitude for Center
Spread, Down Spread or Asymmetric Spread.
• TTL/CMOS compatible outputs.
• 3.3V Operating Voltage.
• 150 ps maximum cycle-to-cycle jitter.
• Available in 16-Pin 150mil SSOP.
DESCRIPTION
The PLL701-50 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
PhaseLink’s unique (Patent Pending) Spread
Spectrum Technology (SST) and permits different
levels of EMI reduction by selecting the amplitude of
the applied SST. The SST feature can be disabled.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x multiplication at
its output.
OUTPUT CLOCK (FOUT) SELECTION
M2
M1
M0
FIN/XIN
(MHz)
Multiplier
FOUT
(MHz)
0 0 0 13 ~ 28
X1
13 ~ 28
0 0 1 13 ~ 28
X2
26 ~ 56
0 1 0 14 ~ 30
X3
42 ~ 90
0 1 1 13 ~ 28
X4
52 ~ 112
1 0 0 20 ~ 30
X5
100 ~ 150
1 0 1 17 ~ 30
X6
102 ~ 180
1 1 0 15 ~ 30
X7
105 ~ 210
1 1 1 13 ~ 28
X8
104 ~ 224
BLOCK DIAGRAM
XIN/FIN
XOUT
SC(0:3)
SD(0:1)
M(0:2)
XTAL
OSC
PLL
SST
OE
Control
Logic
REF
FOUT
DIE PAD CONFIGURATION
69 mil
XOUT/SD0*^
GNDOSC
M2^
M1^
M0^
23
22 21 20
C501A
25 _A2727
-27
28
29
30
18
19
17
16
15
14
13
12
1700, 2540
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
TESTB
SC0^
SC1^
Y
X
33
34
1
35
10
OE^
8
45 6
7
FOUT
GNDBUF
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
104 x 69 mil
GND
80 micron x 80 micron
10 mil
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1