PLL701-10 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – Low EMI Spread Spectrum Multiplier IC (in Die or Package)

PLL701-10
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
FEATURES
• Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
• 13MHz to 240MHz output with output enable.
• 13MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
• Reduced EMI from Spread Spectrum Modulation,
with selectable modulation amplitude for Center
Spread, Down Spread or Asymmetric Spread.
• TTL/CMOS compatible outputs.
• 3.3V Operating Voltage.
• 150 ps maximum cycle-to-cycle jitter.
• Available in 16-Pin 150mil SSOP or DIE.
DESCRIPTION
The PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
different levels of EMI reduction by selecting the
amplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x at its output.
OUTPUT CLOCK (FOUT) SELECTION
M2
M1
M0
FIN/XIN
(MHz)
Multiplier
FOUT
(MHz)
0 0 0 13 ~ 28
X1
13 ~ 28
0 0 1 13 ~ 28
X2
26 ~ 56
0 1 0 14 ~ 30
X3
42 ~ 90
0 1 1 13 ~ 28
X4
52 ~ 112
1 0 0 20 ~ 30
X5
100 ~ 150
1 0 1 17 ~ 30
X6
102 ~ 180
1 1 0 15 ~ 30
X7
105 ~ 210
1 1 1 13 ~ 28
X8
104 ~ 224
BLOCK DIAGRAM
XIN
XOUT
M(0:2)
SD(0:1)
SC(0:3)
XTAL
OSC
PLL
SST
Control
Logic
OE
FOUT
PACKAGE PIN CONFIGURATION
XIN/FIN 1
XOUT/SD0*^ 2
M2^ 3
M1^ 4
M0^ 5
SC0^ 6
SC1^ 7
SC2^ 8
16 GND
15 AVDD
14 REF/SD1*^
13 VDD
12 SC3^
11 OE^
10 FOUT
9 GND
XIN/FIN = 10 ~ 30 MHz
DIE PAD CONFIGURATION
69 mil
XOUT/SD0*^
GNDOSC
M2^
M1^
M0^
23
22 21 20
C501A
25 _A0404
-04A
28
29
30
18
19
17
16
15
14
13
12
1700, 2540
AVDD
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
10
OE^
SC0^
SC1^
34
1
35
8
45 6
7
FOUT
GNDBUF
Y
X
Note:
^: Internal pull-up resistor (120kΩ for SD0, 30 kΩ for SC0-
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
*: SD0 and SD1 are latched upon power-up.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1