PLL701-01 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low EMI Spread Spectrum Multiplier Clock

PLL701-01/02/04/06
Low EMI Spread Spectrum Multiplier Clock
FEATURES
• Spread Spectrum Clock Generator with selectable
multiplier from 1x to 6x outputs.
• Output frequency ranges: 10MHz to 180MHz.
• Accepts input from crystal or reference clock.
• Selectable Center, Down or Asymmetric Spread
Modulation.
• Selectable Modulation rate.
• TTL/CMOS compatible outputs.
• 3.3V Operating Voltage.
• Low short term jitter.
• Available in 8-Pin 150mil SOIC.
DESCRIPTION
The PLL701-01/02/04/06 are Spread Spectrum Clock
Generators designed for the purpose of reducing EMI
in high-speed digital systems. Any output frequency
from 10 to 180MHz can be selected by programming
6 multiplier modes. The device is designed to operate
from a crystal or reference clock input and provides
1x to 6x modulated clock outputs.
OUTPUT CLOCK (FOUT) SELECTION
PIN CONFIGURATION
XIN/FIN 1
XOUT/SD*^ 2
SC0^ 3
SC1^ 4
8 VDD
7 SC2^
6 FOUT
5 GND
XIN/FIN = 10 ~ 30 MHz
Note: ^: Internal pull-up resistor (120kΩ for SD, 30 kΩ for
SC0-SC2).
*: The value of SD is latched upon power-up. The
internal pull-up resistor results in a default high value
when no pull-down resistor is connected to this pin
(recommended external pull-down resistor of 27 kΩ).
SD
SC2
SC1
SC0
FOUT
(-01)
FOUT
(-02)
FOUT
(-04)
FOUT
(-06)
Magnitude
SST Modulation
Freq.
Type
10
0
0
X1
X2
X4
X6
10
0
1
X1
X2
X4
X6
00
0
1
X1
X2
X4
X6
10
1
0
X1
X2
X4
X6
00
1
0
X1
X2
X4
X6
10
1
1
X1
X2
X4
X6
00
1
1
X1
X2
X4
X6
11
0
0
X1
X2
X4
X6
01
0
0
X1
X2
X4
X6
11
0
1
X1
X2
X4
X6
01
0
1
X1
X2
X4
X6
11
1
0
X1
X2
X4
X6
01
1
0
X1
X2
X4
X6
11
1
1
X1
X2
X4
X6
Notes: C: Center Spread. A: Asymmetric Spread. D: Down Spread.
0.50%
1.00%
1.50%
2.00%
2.50%
3.00%
3.50%
OFF
C
±0.25%
C
±0.5%
D
-1.0%
C
±0.75%
A +0.25% ~ -1.25%
C
±1.0%
Fin / 512 ^{A +0.5% ~ -1.5%}
C
±1.25%
A +0.75% ~ -1.75%
C
±1.5%
A +1.0% ~ -2.0%
C
±1.75%
A +1.25% ~ -2.25%
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone] www.phaselink.com Rev 08/30/05 Page 1