PLL650-10 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Network LAN Clock for Gigabit Ethernet

PRELIMINARY PLL650-10
Network LAN Clock for Gigabit Ethernet
FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• Two outputs fixed at 125MHz..
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 8-Pin 150mil SOIC.
PIN CONFIGURATION
XIN 1
XOUT 2
GND 3
125MHz 4
8 VDD
7 GND
6 VDD
5 125MHz
DESCRIPTIONS
The PLL 650-10 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25MHz crystal, and produces multiple output
clocks for networking chips, and ASICs.
BLOCK DIAGRAM
XIN
XO UT
XTAL
OSC
C o n tro l
Lo g ic
1 2 5 MHz
1 2 5 MHz
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 12/10/02 Page 1