PLL650-09 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Cost Network LAN Clock

FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 4 outputs fixed at 50MHz .
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 16-Pin 150mil SOIC.
DESCRIPTIONS
The PLL 650-09 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips.
PLL650-09
Low Cost Network LAN Clock
PIN CONFIGURATION
XIN
1
XOUT 2
GND 3
VDD 4
50MHz 5
GND 6
50MHz 7
50MHz 8
16 VDD
15 VDD
14 N/C
13 GND
12 GND
11 GND
10 VDD
9 50MHz
BLOCK DIAGRAM
XIN
XO UT
XTAL
OSC
C o n tro l
Lo g ic
4
5 0 MHz
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Rev 09/19/02 Page 1