PLL650-08 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Network LAN Clock Source

FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 1 output fixed at 100MHz , 1 output fixed at 125MHz .
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 8-Pin 150mil SOIC.
DESCRIPTIONS
The PLL 650-08 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25MHz crystal, and produces multiple output
clocks for networking chips, and ASICs.
PRELIMINARY PLL650-08
Network LAN Clock Source
PIN CONFIGURATION
XIN 1
XOUT 2
GND 3
VDD 4
8 VDD
7 100MHz
6 GND
5 125MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
Control
Logic
100MHz
125MHz
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Rev 07/15/02 Page 1