PLL650-07 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – LOW COST Network LAN Clock SOURCE

PLL650-07
LOW COST Network LAN Clock SOURCE
FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz .
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 14-Pin 150mil SOIC.
DESCRIPTION
The PLL650-07 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-07 an
excellent choice for systems requiring clocking for network
chips and ASICs.
BLOCK DIAGRAM
PIN CONFIGURATION
XOUT 1
GNDA 2
VDD50M 3
50MHz 4
GND50M 5
50MHz 6
VDD25M 7
14 XIN
13 VDDA
12 NC
11 GND
10 25MHz
9 GND25M
8 25MHz
XIN
XOUT
XTAL
OSC
Phase
Detector
Charge
Pump
+
Loop
Filter
VCO
VCO
Divider
Post
Divider
2 _50MHz
2 _25MHz
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1