PLL650-06 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Network LAN Clock

FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• One output fixed at 50MHz
• One selectable frequency output of 66.6 or 75MHz (with
Double Drive Strength output).
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 8-Pin 150mil SOIC.
DESCRIPTION
The PLL 650-06 is a low cost, low jitter, and high
performance clock synthesizer. Using PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce one 50MHz output clock and one
selectable 75MHz or 66.6MHz output clock from a single
low cost 25.0MHz crystal. This makes the PLL650-06 ideal
for networking applications.
PLL650-06
Network LAN Clock
PIN CONFIGURATION
XIN 1
XOUT 2
GND 3
50MHz/FS* 4
8 VDD
7 GND
6 75MHz⁺/66MHz⁺
5 VDD
*: bi-directional pin + : double strength output
FREQUENCY TABLE
FS
0
1
Pin 6
75MHz
66.6MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
FS
Control
Logic
50MHz
1
75MHz/66MHz
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1