PLL650-05 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – Low EMI Network LAN Clock

FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with
output disable
• SDRAM selectable frequencies of 105, 83.3, 140MHz
(Double Drive Strength).
• Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% center for SDRAM and
CPU.
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 16-Pin 150mil SOIC.
DESCRIPTION
The PLL650-05 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-05 an
excellent choice for systems requiring clocking for network
chips, PCI devices, SDRAM, and ASICs.
BLOCK DIAGRAM
PLL650-05
Low EMI Network LAN Clock
PIN CONFIGURATION
XIN
1
XOUT/ENB_125M*^ 2
GND 3
VDD 4
125MHz 5
GND 6
75MHz/FS1*^ 7
ENB_75MHz^ 8
16 VDD
15 VDD
14 25MHz/FS0*^
13 GND
12 GND
11 SDRAMx2
10 VDD
9 SS0^T
Note: SDRAMx2: Double Drive strength. ^T: Tri-Level input ^: Internal pull-up
resistor *: Bi-directional pin (input value is latched upon power-up).
FREQUENCY TABLE
FS1 FS0
0
0
0
1
1
0
1
1
SDRAMX2
Tristate
140MHz^SST
83.3MHz^SST
105MHz^SST
XIN
XOUT
XTAL
OSC
FS (0:1)
Control
Logic
1
125MHz
(can be disabled)
1
SDRAM (105, 83.3, 140MHz)
1
75 MHz
(can be disabled)
1
25MHz
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1