PLL650-04 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – Low EMI Clock for 10/100 PHY and Gigabit Ethernet

Preliminary PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
FEATURES
• Full CMOS output swing with 25-mA output drive
capability at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25 MHz fundamental crystal or clock input.
• Low jitter (< 80ps cycle-to-cycle)
• 25 MHz and 50 MHz outputs
• Five CLKOUT selectable between 90, 100, 125, 133,
145 and 150 MHz.
• SSTE (SST Enable) Low EMI selector for CLKOUT.
• Output enable functionality.
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 20-Pin 150mil SSOP.
DESCRIPTION
The PLL650-04 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink proprietary
analog Phase Locked Loop techniques, the chip accepts
25.0 MHz crystal, and produces multiple output clocks for
networking chips. A CLKOUT signal of selectable
frequency (25MHz, 48MHz, 50MHz, 90MHz, 100MHz,
125MHz, 133MHz, 145MHz or 150 MHz) is available at 5
output pins. Through an SST enable (SSTE) selector, the
CLKOUT signal can be modulated to reduce EMI through
Spread Spectrum Technology. Output enable selectors are
available to enable/disable the output signals.
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
FS (0:1)
SSTE
(SST enable)
Control
Logic
PIN CONFIGURATION
XIN 1
XOUT/SSTE*^ 2
GND 3
VDD 4
CLKOUT_EN^ 5
VDD 6
CLKOUTº 7
CLKOUTº 8
FS1^ 9
CLKOUTº 10
20 VDD
19 50M_EN^
18 25MHz/25M_EN*^
17 GND
16 50MHz
15 GND
14 CLKOUTº
13 FS0
12 CLKOUTº
11 GND
Note: ^: Internal pull-up resistor *: Bi-directional pin º: Low EMI output
SELECTION TABLE
FS1 FS0 CLKOUT
0
0 90 MHz
0
M 100 MHz
0
1 125 MHz
1
0 133 MHz
1
M 145 MHz
1
1 150 MHz
Tri-level input pins: 0 = connect to GND
M= not connected, 1 = connect to VDD
SSTE
0
1
SST
MODULATION
±0.25% Center
OFF
25M_EN (enable)
1
25MHz
50M_EN (enable)
1
50MHz
CLKOUT_EN (enable)
5
CLKOUT (90 100, 125, 133,
145 or 150 MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 05/31/05 Page 1