PLL650-03 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – Low EMI Network LAN Clock

PLL650-03
Low EMI Network LAN Clock
FEATURES
• Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
• Advanced, low power, sub-micron CMOS processes.
• 25MHz fundamental crystal or clock input.
• 4 outputs fixed at 50MHz with output disable, 1 output
selectable at 25MHz or 100MHz with output disable
• SDRAM selectable frequencies of 66.6, 75, 83.3, 100MHz
(Double Drive Strength).
• Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% center for SDRAM and
CPU.
• Zero PPM synthesis error in all clocks.
• Ideal for Network switches.
• 3.3V operation.
• Available in 16-Pin 150mil SOIC.
DESCRIPTION
The PLL 650-03 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs.
BLOCK DIAGRAM
PIN CONFIGURATION
XIN
1
XOUT/50MHz_OE*^ 2
GND 3
VDD 4
50MHz/FS0*^ 5
GND 6
50MHz/FS1*^ 7
50MHz/FS2* ^T 8
16 VDD
15 VDD
14 25MHz/100MHz
13 GND
12 GND
11 SDRAMx2
10 VDD
9 50MHz/SS0* ^T
Note: SDRAMx2: Double Drive strength. ^T: Tri-Level input ^: Internal pull-up
resistor *: Bi-directional pin (input value is latched upon power-up).
FREQUENCY TABLE
FS0 FS1
0
0
0
1
1
0
1
1
SDRAM
100MHz^SST
83.3MHz^SST
75MHz^SST
66.6MHz^SST
FS2
Pin 14
0
25MHz
M
Disable
1
100MHz^SST
SST: SST modulation applied
XIN
XOUT
XTAL
OSC
FS (0:3)
Control
Logic
4
50MHz
(can be disabled)
1
SDRAM (66.6, 75, 83.3, 100MHz)
1
25MHz/100 MHz
(can be disabled)
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1