PLL650-01 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low EMI Network LAN Clock

FEATURES
• Full CMOS output swing with 25 mA output drive
capability at TTL levels.
• Advanced, low power, sub-micron CMOS
process.
• 25.0MHz fundamental crystal or reference clock
signal.
• Six output clocks with selectable frequencies.
• SDRAM frequencies of 67,83,100, and 133MHz.
• Spread Spectrum Technology selectable for EMI
Reduction from ±0.25% to ±0.5% center.
• Buffered crystal reference output.
• Ideal for Network switches.
• 3.3V operation.
• Available in 150mil 20-Pin SSOP.
DESCRIPTION
The PLL650-01 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques,
the chip accepts 25.0MHz from a crystal or a refer-
ence clock, and produces multiple outputs clocks for
network chips, PCI devices, SDRAM, and ASICs.
PLL650-01
Low EMI Network LAN Clock
PIN CONFIGURATION
FS0 1
XOUT 2
XIN 3
VDD 4
FS1 5
GND 6
CLKC1 7
CLKC2 8
CLKB2 9
CLKB1 10
20 FS3
19 FS2
18 REF/CS1*^
17 CLKA1
16 VDD
15 OE^
14 GND
13 CLKA2
12 FS4
11 CS0
Note:
^: 100kΩ internal pull-up. *: Bi-directional pin. The value of
CS1 is latched upon power-up. When no external pull-down re-
sistor is connected to the pin, the internal pull-up results in a
default high value for CS1. An external 10kΩ pull-down resis-
tor is recommended to set CS1 to low.
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
FS (0:4)
CS (0:1)
OE
Control
Logic
REFOUT
CLKA1
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1