PLL620-80 Datasheet, PDF (1/7 Pages) List of Unclassifed Manufacturers – Low Phase Noise XO (9.5-65MHz Output)

PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
FEATURES
• 19MHz to 65MHz crystal input.
• Output range: 9.5MHz – 65MHz
• Selectable OE Logic (enable high or enable low).
• Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
• Supports 2.5V or 3.3V Power Supply.
• Available in die form.
DIE CONFIGURATION
65 mil
(1550,1475)
25
24 23 22 21
20
19
18
17 GNDBUF
XIN 26
XOUT 27
Die ID:
A2020-20B
16 CMOS
15 LVDSB
N/C 28
14 PECLB
DESCRIPTION
The PLL620-80 is a XO IC specifically designed to
work with fundamental or 3^rd OT crystals between
19MHz and 65MHz. The selectable divide by two
feature extends the operation range from 9.5MHz to
65MHz. It requires very low current into the crystal
resulting in better overall stability. The OE logic
feature allows selection of enable high or enable low.
Furthermore, it provides selectable CMOS, PECL or
LVDS outputs.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
Oscillator
XIN ^Amplifier
XOUT
OE
Q
Q
S2
PLL620-80
S2^ 29
13 VDDBUF
12 VDDBUF
OE
CTRL ³⁰
11 PECL
C502A
10 LVDS
N/C 31
9 OE_SEL^
12345
6
78
Y ^(0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* OUT_SEL0*
(Pad 18)
(Pad 25)
Selected Output*
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
LVDS
1
1
PECL (default)
OE_SELECT
(Pad 9)
0
1 (Default)
OE_CTRL
(Pad 30)
0
1 (Default)
0 (Default)
1
State
Tri-state
Output enabled
Output enabled
Tri-state
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
OUTPUT FREQUENCY SELECTOR
S2
0
1(Default)*
Output
Input/2
Input
*Internally set to ‘Default’ through 60K pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/09/04 Page 1