PLL620-30 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
FEATURES
• 65MHz to 130MHz Crystal input.
• Output range: 32.5MHz – 130MHz (no PLL).
• Low Injection Power for crystal, 50uW.
• Complementary outputs: PECL or LVDS.
• Selectable OE Logic
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTION
The PLL620-30 is a XO IC specifically designed to
drive fundamental or 3^rd OT crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability.
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
XIN 26
XOUT 27
Die ID:
A2020-20A
N/C 28
S2^ 29
OE
CTRL
30
N/C 31
C502A
1 23 4 5
6
78
(1550,1475)
17 GNDBUF
16 N/C
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OUTSEL^
Y ^(0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
Oscillator
XIN ^Amplifier
XOUT
OE
Q
Q
PLL620-30
OUTPUT SELECTION AND ENABLE
OUTSEL
(Pad #9)
0
1
Selected Output
LVDS
PECL (default)
OESEL
(Pad #25)
0
1 (default)
OE_CTRL
(Pad #30)
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Pad #9, #25: Bond to GND to set to “0”. Internal pull up.
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
OUTPUT FREQUENCY SELECTOR
S2
0
1(Default)*
Output
Input/2
Input
*Internally set to ‘Default’ through 60K pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/09/04 Page 1