PLL620-21 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Phase Noise XO (for HF Fund. and 3-rd O.T.)

Preliminary PLL620-21
Low Phase Noise XO (for HF Fund. and 3^rd O.T.)
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication).
• Selectable OE logic.
• Minimum bondwires required for VDD and GND.
• Available outputs: PECL or LVDS.
• Supports 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTIONS
PLL620-21 is an XO IC specifically designed to work
with high frequency fundamental and third overtone
crystals. Its design was optimized to tolerate higher
limits of interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It offers a selectable OE logic and is ideal
for XO applications requiring LVDS or PECL output
levels at high frequencies.
BLOCK DIAGRAM
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DIE CONFIGURATION
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DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
0
1
Selected Output
LVDS
PECL (default)
Pad #25 Pad #30
OESEL OE_CTRL
State
0
0
Tri-state
1
Output enabled (default)
1
0
Output enabled (default)
(default)
1
Tri-state
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OUTSEL (pad #9) is “1”
Logical states defined by CMOS levels if OUTSEL is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone] www.phaselink.com Rev 07/15/05 Page 1