PLL620-20 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Phase Noise XO (for HF Fund. and 3rd O.T.)

PLL620-20
Low Phase Noise XO (for HF Fund. and 3^rd O.T.)
FEATURES
• 100MHz to 200MHz Fund. or 3^rd OT Crystal.
• Output range: 100 – 200MHz (no multiplication).
• Available outputs: PECL, or LVDS.
• OESEL/OECTRL for both PECL & LVDS.
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Die thickness 10 mil.
DESCRIPTION
The PLL620-20 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
X+
Oscillator
X- ^Amplifier
OE
Q
Q
PLL620-20
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
XIN 26
XOUT 27
Die ID:
A1212-12
N/C 28
N/C 29
OE
CTRL ³⁰
N/C 31
C502A
1 23 4 5
6
78
(1550,1475)
17 GNDBUF
16 N/C
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OUTSEL^
Y ^(0,0)
X
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
0
1
Selected Output
LVDS
PECL (default)
Pad #9
OUTSEL
0
Pad #30
OE_CTRL
0
1
State
Tri-state
Output enabled (default)
1
0
Output enabled (default)
1
Tri-state
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OUTSEL is “1”
Logical states defined by CMOS levels if OUTSEL is “0”
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1