PLL620-05 Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)

PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
FEATURES
• 100MHz to 200MHz Fundamental or 3^rd
Overtone Crystal.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x
multiplier).
• CMOS (Standard drive PLL620-07 or Selectable
Drive PLL620-06), PECL (Enable low PLL620-08
or Enable high PLL620-05) or LVDS output
(PLL620-09).
• Supports 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL620-06 only available in 3x3mm.
Note: PLL620-07 only available in TSSOP.
PIN CONFIGURATION
(Top View)
VDD 1
XIN 2
XOUT 3
SEL3^ 4
SEL2^ 5
OE 6
GND 7
GND 8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
DESCRIPTION
The PLL620-0x family of XO IC’s is specifically
designed to work with high frequency fundamental
and third overtone crystals. Their low jitter and low
phase noise performance make them well suited for
high frequency XO requirements. They achieve very
low current into the crystal resulting in better overall
stability.
BLOCK DIAGRAM
SEL
OE
PLL
(Phase
Q
Oscillator
X+ ^Amplifier
Locked
Loop)
Q
X-
PLL by-pass
XIN
XOUT
SEL2^
OE
12 11 10
13
9
8
14
PLL620-0x
7
15
6
16
5
123 4
GND
CLKC
VDD
CLKT
^: Internal pull-up
*: PLL620-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PLL620-08
0
(Default)
1
Output enabled
Tri-state
PLL620-05
PLL620-06
PLL620-07
PLL620-09
0
1
(Default)
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL620-08
Logical states defined by CMOS levels for PLL620-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/01/05 Page 1