PLL620-00 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.)

PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3^rd O.T.)
FEATURES
• 100MHz to 200MHz Fundamental or 3^rd
Overtone Crystal input.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier) or 400 – 700MHz
(4x multiplier).
• Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
• Supports 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTION
The PLL620-00 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
SEL
Vin
Oscillator
X+ ^Amplifier
X-
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PLL620-00
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
XIN 26
XOUT 27
Die ID:
A1010-10A
SEL3^ 28
SEL2^ 29
OE
CTRL ³⁰
NC 31
C502A
1 23 4 5
6
78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y ^(0,0)
X
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
OE_SELECT
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
State
Tri-state
Output enabled
Output enabled
Tri-state
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad
#9) is “1”
Logical states defined by CMOS levels if OE_SELECT is
“0”
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1