PLL602-42 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise CMOS XO (96MHz to 190MHz)

PLL602-42 Preliminary for proposal
Low Phase Noise CMOS XO (96MHz to 190MHz)
FEATURES
• Low phase noise XO for the 96MHz to 190MHz
range (-133 dBc at 10kHz offset).
• CMOS output.
• 12 to 24MHz crystal input.
• Integrated crystal load capacitor: no external
load capacitor required.
• Low jitter (RMS): 3-6ps period, 7-10ps accum.
• 3.3V operation.
• Available in 8-Pin TSSOP or SOIC.
DESCRIPTIONS
The PLL602-42 is a low cost, high performance and
low phase noise XO, providing less than -133 dBc at
10kHz offset in the 96MHz to 190MHz operating
range. The very low jitter (3 to 6 ps RMS period jitter
and 6 to 10 ps RMS accumulated jitter) makes this
chip ideal for 155.52MHz SONET and SDH applica-
tions, and for 125MHz and 106.25MHz applications.
Input crystal can range from 12 to 24MHz (funda-
mental resonant mode).
BLOCK DIAGRAM
PIN CONFIGURATION
CLK 1
VDD 2
OE 3
XIN 4
8 GND
7 GND
6 N/C
5 XOUT
OUTPUT RANGE
MULTIPLIERS
FREQUENCY
RANGE
x8
96 - 190MHz
OUTPUT
BUFFER
CMOS
Reference
Divider
XIN
XOUT
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 07/13/01 Page 1