PLL602-38N Datasheet, PDF (1/4 Pages) PhaseLink Corporation – 4x Low Phase Noise Multiplier PECL XO

PLL602-38N
4x Low Phase Noise Multiplier PECL XO
Universal Low Phase Noise IC
FEATURES
• Low phase noise output (-127dBc @ 10kHz fre-
quency offset).
• 12MHz to 25MHz crystal input.
• 48MHz to 100MHz PECL output.
• 3.3V operation.
• Available in Green (RoHS Compliant) 8-Pin
SOIC package.
DESCRIPTION
The PLL602-38N is a high performance and low
phase noise PECL XO IC chip. It provides phase
noise performance as low as –127dBc at 10kHz off-
set and a typical RMS jitter of 4.5pS RMS ( at
100MHz ). It accepts a fundamental parallel reso-
nant mode crystal input from 12MHz to 25MHz.
PIN CONFIGURATION
(Top View)
X1 1
X2 2
GND 3
GND 4
8 VDD
7 CLKB
6 VDD
5 CLK
BLOCK DIAGRAM
XIN
PLL
Q
Oscillator
XOUT Amplifier
(Phase
Locked
Q
Loop)
PLL602-38N
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/24/04 Page 1