PLL602-35 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – 750kHz -800MHz Low Phase Noise Multiplier XO

PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FEATURES
• Selectable 750kHz to 800MHz range.
• Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
110dBc/Hz for 622.08MHz).
• CMOS (PLL602-37), PECL (PLL602-35 and
PLL602-38) or LVDS (PLL602-39) output.
• 12 to 25MHz crystal input.
• No external load capacitor required.
• Output Enable selector.
• Selectable 1/16 to 32x frequency multiplier.
• 3.3V operation.
• Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
VDD 1
XIN 2
XOUT 3
SEL3^ 4
SEL2^ 5
OE 6
GND 7
GND 8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
DESCRIPTION
The PLL602-35 (PECL with inverted OE), PLL602-37
(CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS)
are high performance and low phase noise XO IC
chips. They provide phase noise performance as low
as –125dBc at 1kHz offset (at 155MHz) and a typical
RMS jitter of 4pS RMS ( at 155MHz ). They accept
fundamental parallel resonant mode crystals from 12
to 25MHz.
BLOCK DIAGRAM
SEL
Oscillator
XIN ^Amplifier
PLL
(Phase
Locked
Loop)
XOUT
PLL by-pass
OE
Q
Q
PLL602-3x
XOUT
SEL3^
SEL2^
OE
12 11 10
13
9
8
14 _PLL602-3X 7
15
6
16
5
123 4
GND
CLKC
VDD
CLKT
^: Internal pull-up
*: On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL602-38
PLL602-35
PLL602-37
PLL602-39
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL602-38
Logical states defined by CMOS levels for
PLL602-35/-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/28/05 Page 1