PLL602-30 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – 750kHz - 800MHz Low Phase Noise XO (for 12 - 25MHz Crystals)

PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
• 750kHz to 800MHz output range.
• Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -123dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
115dBc/Hz for 622.08MHz).
• Selectable CMOS, PECL and LVDS output.
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• 12MHz to 25MHz crystal input.
• Output Enable selector.
• 3.3V operation.
• Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL602-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) XO IC
Die, with selectable CMOS, LVDS or PECL output,
covering the 750kHz to 800MHz output range, using
a low frequency crystal.
This makes the PLL602-30 ideal as a universal die
for applications ranging from low frequency to
SONET.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
DIE CONFIGURATION
65 mil
(1550,1475)
25
24 23 22 21
20
19
18
17 GNDBUF
XIN 26
XOUT 27
Die ID:
A1414-14E
16 CMOS
15 LVDSB
SEL3 28
14 PECLB
SEL2 29
13 VDDBUF
12 VDDBUF
OE_CTRL 30
C502A
11 PECL
10 LVDS
N/C 31
9 OE_SEL^
12345
6
78
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
Selected Output
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
PECL
1
1
LVDS
OE_SELECT
(Pad #9)
0
OE_CTRL
(Pad #30)
0 (Default)
1
State
Output enabled
Tri-state
1 (Default)
0
Tri-state
1 (Default) Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
SEL
XIN
XOUT
Reference
Divider
XTAL
OSC
VCO
Divider
Phase
Detector
Charge
Pump
+
Loop
Filter
VCO
OE
CLKBAR
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1