PLL602-10 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – 96MHz - 400MHz Low Phase Noise XO (for 12 - 25MHz Crystals)

Preliminary PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
• Low phase noise output for the 96MHz to
400MHz range (-134 dBc at 10kHz offset).
• Selectable CMOS, PECL and LVDS output.
• 12 to 25MHz crystal input.
• Output Enable selector.
• 3.3V operation.
• Available in DIE (65 mil x 62 mil).
DESCRIPTIONS
The PLL602-10 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
Die, with CMOS, LVDS and PECL output, for 96MHz
to 400MHz output range, using a low frequency
crystal.
The same die can be used as a XO with output
frequencies ranging from FXIN x 8 to FXIN x 16 thanks
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL602-10 ideal for a wide range of applications.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
DIE CONFIGURATION
65 mil
(1550,1475)
25
24 23 22 21
20
19
18
17
26
16
15
27
14
28
13
29
12
11
30
10
31
9
1
23
4
5
6
78
Y
(0,0)
X
MULTIPLIER SELECTION
Pad #19
0
1
MULTIPLIER
FXIN x 16
FXIN x 8
OUTPUT RANGE
192 – 400 MHz
96 – 200 MHz
Note: Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
OE (Pad #30)
0
1 (Default)
State
Tri-state
Output enabled
SELECT
XIN
XOUT
Reference
Divider
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLKBAR
CLK
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Rev 11/06/02 Page 1