PLL602-04 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise CMOS XO (96MHz to 200MHz)

PLL602-04
Low Phase Noise CMOS XO (96MHz to 200MHz)
FEATURES
• Low phase noise XO for the 96MHz to 200MHz
range (-125 dBc at 10kHz offset).
• 12 to 25MHz crystal input.
• Integrated crystal load capacitor: no external
load capacitor required.
• Low jitter (RMS): 4ps period jitter (1 sigma).
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• 3.3V operation.
• Available in 8-Pin TSSOP or SOIC.
DESCRIPTION
The PLL602-04 is a low cost, high performance and
low phase noise XO, providing less than -125 dBc at
10kHz offset in the 96MHz to 200MHz operating
range. The very low jitter (4ps RMS period jitter)
makes this chip ideal for 155.52MHz SONET and
SDH applications, and for 125MHz and 106.25MHz
applications. Input crystal can range from 12 to
25MHz (fundamental resonant mode).
BLOCK DIAGRAM
PIN CONFIGURATION
CLK 1
VDD 2
OE^ 3
XIN 4
8 GND
7 GND
6 N/C
5 XOUT
Note: ^ denotes internal pull up
OUTPUT RANGE
MULTIPLIER
x8
FREQUENCY
RANGE
96 - 200MHz
OUTPUT
BUFFER
CMOS
Reference
Divider
XIN
XOUT
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1